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| 1 of 104 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 3gb/s, hd, sd sdi receiver , with integrated adaptive cable equalizer complete with smpte video processing GS2961A www.semtech.com key features ? operation at 2.97gb/s, 2.97/1.001gb/s, 1.485gb/s, 1.485/1.001gb/s and 270mb/s ? supports smpte 425m (level a and level b), smpte 424m, smpte 292m, smpte 259m-c and dvb-asi ? integrated adaptive cable equalizer ? typical equalized length of belden 1694a cable: ? 150m at 2.97gb/s ? 250m at 1.485gb/s ? 480m at 270mb/s ? integrated reclocker with low phase noise, integrated vco ? serial digital reclocked, or non-reclocked output ? ancillary data extraction ? optional conversion from smpte 425m level b to level a for 1080p 50/60 4:2:2 10-bit ? parallel data bus selectable as either 20-bit or 10-bit ? comprehensive error detection and correction features ? output h, v, f or cea 861 timing signals ? 1.2v digital core power supply, 1.2v and 3.3v analog power supplies, and selectable 1.8v or 3.3v i/o power supply ? gspi host interface ? wide temperature range of -40oc to +85oc ? low power operation (typically 515mw) ? small 11mm x 11mm 100-ball bga package ? pb-free and rohs compliant applications description the GS2961A is a multi-rate sd i integrated receiver which includes complete smpte processing, as per smpte 425m, 292m and smpte 259m-c. the sm pte processing features can be bypassed to support signals with other coding schemes. the GS2961A integrates ge nnum's adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. it features dc restoration to compensate for the dc content of smpte pathological signals. the device features an integrated reclocker with an internal vco and a wide input jitter tolerance (ijt) of 0.7ui. hd-sdi application: single link (3g-sdi) to dual link (hd-sdi) converter gs2962 link a link b hv f/pclk 10-bit 3g-sdi GS2961A gs2962 10-bit hv f/pclk hd-sdi application: dual link (hd-sdi) to single link (3g-sdi) converter hd-sdi deserializer GS2961A link a fifo wr deserializer link b fifo wr gs2962 gs4910 10-bit 3g-sdi hvf xtal hv f/pclk hv f/pclk hv f/pclk GS2961A 10-bit 10-bit 10-bit hd-sdi hd-sdi hd-sdi
GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 2 of 104 a serial digital loop-through output is provided, which can be configured to output either reclocked or non-reclocked serial digital data. the serial digital output can be connected to an external cable driver. the device operates in one of four basic modes: smpte mode, dvb-asi mode, data-through mode or standby mode. in smpte mode (the default operating mode ), the GS2961A performs full smpte processing, and features a number of data integrity checks and measurement capabilities. the device also supports ancillary data extraction, and can provide entire ancillary data packets through host-accessible registers. it also provides a variety of other packet detection and error handling features. all of these processing features are optional, and may be individually enabled or disabled through register programming. both smpte 425m level a and le vel b inputs are supported with optional conversion from level b to level a for 1080p 50/59.94/60 4:2:2 10-bit inputs. in dvb-asi mode, sync word detection, alignment and 8b/10b decoding is applied to the received data stream. in data-through mode all forms of smpte and dvb-asi processing are disabled, and the device can be used as a simple serial to parallel converter. the device can also operate in a lower power standby mode. in this mode, no signal processing is carried out and the parallel output is held static. parallel data outputs are provided in 20-bit or 10-bit format for 3gb/s, hd and sd video rates, with a variety of mapping options. as such, this parallel bus can interface directly with video processor ics, and output data can be multiplexed onto 10 bits for a low pin count interface. functional block diagram GS2961A functional block diagram buffer mux reclocker with integrated vco sdi sdo sdo serial to parallel converter descramble, word align, rate detect flywheel video standard detect trs detect timing extraction mux dvb-asi decoder illegal code remap, trs/ line number/ crs insertion, edh packet insertion v/vsync h/hsync f/de rate_det[1:0] anc/ checksum /352m extraction error flags yanc/canc locked dvb_asi standby gspi and jtag controller host interface output mux/ demux crystal buffer/ oscillator lf lb_cont vbg rc_byp i/o control tim861 20bit/10bit smpte_bypass ioproc_en/dis reset_trst core_vdd core_gnd io_vdd io_gnd sdo_en/dis cs_tms sclk_tclk sdin_tdi sdout_tdo jtag/host xtal1 sw_en vco_vdd vco_gnd pll_vdd pll_gnd eq_vdd eq_gnd a_vdd a_gnd buff_vdd buff_gnd buffer sdi xtal2 xtal_out smpte 425m 1080p 50/60 4:2:2 10-bit level b level a eq agc+ agc- dout[19:0] pclk locked GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 3 of 104 contents key features ................................................................................................................... .....................................1 applications................................................................................................................... ......................................1 description.................................................................................................................... .......................................1 functional block diagram ..................................... .................................................................. .......................2 1. pin out..................................................................................................................... ..........................................7 1.1 pin assignment ............................................................................................................ ......................7 1.2 pin descriptions .......................................................................................................... ......................7 2. electrical characteristics .................................................................................................. ....................... 14 2.1 absolute maximum ratings .................................................................................................. ..... 14 2.2 recommended operating conditions ..... ........... .......... ........... ........... ........... ........... ......... ..... 14 2.3 dc electrical characteristics ...... ....................................................................................... ........ 15 2.4 ac electrical characterist ics ............................................................................................. ........ 17 3. input/output circuits ....................................................................................................... ........................ 22 4. detailed description........................................................................................................ .......................... 26 4.1 functional overview ....................................................................................................... ............. 26 4.2 smpte 425m mapping - 3g level a and level b formats ............................................... 27 4.2.1 level a mapping.......................................................................................................... ...... 27 4.2.2 level b mapping .......................................................................................................... ...... 27 4.3 serial digital input ...................................................................................................... .................. 28 4.3.1 integrated adaptive cable equalizer.......................................................................... 28 4.4 serial digital loop-through output ........................................................................................ 29 4.5 serial digital reclocker .................................................................................................. ............. 29 4.5.1 pll loop bandwidth ....................................................................................................... .30 4.6 external crystal/reference clock .......................................................................................... .30 4.7 lock detect ............................................................................................................... ....................... 32 4.7.1 asynchronous lock ........................................................................................................ .. 32 4.7.2 signal interruption ...................................................................................................... ...... 33 4.8 smpte functionality ....................................................................................................... ............. 33 4.8.1 descrambling and word alignment ................. .......................................................... 33 4.9 parallel data outputs ..................................................................................................... .............. 34 4.9.1 parallel data bus buffers................................................................................................ .34 4.9.2 parallel output in smpte mode ................................................................................... 37 4.9.3 parallel output in dvb-asi mode ............................................................................... 37 4.9.4 parallel output in data-through mode ..................................................................... 38 4.9.5 parallel output clock (pclk)......................................................................................... 38 4.9.6 ddr parallel clock timing ............................................................................................. 39 4.10 timing signal generator .................................................................................................. ......... 41 4.10.1 manual switch line lock handling.......................................................................... 42 4.10.2 automatic switch line lock handling .................................................................... 43 4.10.3 switch line lock handling during level b to level a conversion ............... 43 4.11 programmable multi-function outputs ............................................................................... 45 4.12 h:v:f timing signal generation ........................................................................................... .46 4.12.1 cea-861 timing generation ....................................................................................... 48 4.13 automatic video standards detection ................................................................................ 55 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 4 of 104 4.13.1 2k support.............................................................................................................. ........... 59 4.14 data format detection & indication ..................................................................................... 60 4.15 edh detection ............................................................................................................ .................. 61 4.15.1 edh packet detection ................................................................................................... 6 1 4.15.2 edh flag detection ...................................................................................................... .. 61 4.16 video signal error detection & indication ......................................................................... 62 4.16.1 trs error detection ..................................................................................................... ... 63 4.16.2 line based crc error detection ................................................................................ 63 4.16.3 edh crc error detection............................................................................................. 64 4.16.4 hd & 3g line number error detection ................................................................... 64 4.17 ancillary data detection & indication ................................................................................. 65 4.17.1 programmable ancillary data detection................................................................ 66 4.17.2 smpte 352m payload identifier ................................................................................ 67 4.17.3 ancillary data checksum error ................................................................................. 68 4.17.4 video standard error.................................................................................................... .69 4.18 signal processing ........................................................................................................ ................. 70 4.18.1 trs correction & insertion........................................................................................... 71 4.18.2 line based crc correction & insertion ................................................................... 71 4.18.3 line number error correction & insertion ............................................................. 71 4.18.4 anc data checksum error correction & insertion ............................................. 71 4.18.5 edh crc correction & insertion ............................................................................... 71 4.18.6 illegal word re-mapping ............................................................................................. 72 4.18.7 trs and ancillary data preamble remapping...................................................... 72 4.18.8 ancillary data extraction............................................................................................. 72 4.18.9 level b to level a conversion .................................................................................... 76 4.19 gspi - host interface .................................................................................................... ............ 77 4.19.1 command word descript ion ............... ........... ........... ........... ........... ........... ........... ..... 78 4.19.2 data read or write access........................................................................................... 78 4.19.3 gspi timing............................................................................................................. .......... 79 4.20 host interface register maps ............................................................................................. ..... 81 4.21 jtag test operation ...................................................................................................... ............ 95 4.22 device power-up .......................................................................................................... ............... 96 4.23 device reset ............................................................................................................. ..................... 97 4.24 standby mode ............................................................................................................. ................. 97 5. application reference design ................................................................................................ ............... 98 5.1 high gain adaptive cable equalizers .................................................................................... 98 5.2 pcb layout ................................................................................................................ ....................... 98 5.3 typical application circuit ............................................................................................... ......... 99 6. references & relevant standards ............................................................................................. .......... 100 7. package & ordering information .............................................................................................. .......... 101 7.1 package dimensions ........................................................................................................ ........... 101 7.2 packaging data ............................................................................................................ ................. 102 7.3 marking diagram ........................................................................................................... .............. 102 7.4 solder reflow profiles .................................................................................................... ............ 103 7.5 ordering information ...................................................................................................... ........... 103 revision history ............................................................................................................... ............................. 103 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 5 of 104 list of figures figure 3-1: digital input pin with schmitt trigger........... .......... ........... ........... ......... ......... ......... ....... .. 22 figure 3-2: bidirectional digital input/output pin............................................................................. .22 figure 3-3: bidirectional digital input/output pin with programmable drive strength ........ 23 figure 3-4: xtal1/xtal2/xtal-out .............................................................................................. ..... 23 figure 3-5: vbg ............................................................................................................... ............................... 24 figure 3-6: lb_cont ........................................................................................................... ......................... 24 figure 3-7: loop filter ....................................................................................................... ........................... 24 figure 3-8: sdo/sdo ............................................................................................................................... ..... 25 figure 3-9: equalizer input equivalent circuit ............. ................................................................... .... 25 figure 4-1: level a mapping ................................................................................................... ................... 27 figure 4-2: level b mapping ................................................................................................... ................... 27 figure 4-3: GS2961A integrated eq block diagram .......... ................................................................ 28 figure 4-4: 27mhz clock sources ............................... ................................................................ ............. 31 figure 4-5: pclk to data and cont rol signal output timing - sdr mode 1 .............................. 34 figure 4-6: pclk to data and cont rol signal output timing - sdr mode 2 .............................. 35 figure 4-7: pclk to data and cont rol signal output timing - ddr mode ................................. 36 figure 4-8: ddr video interface - 3g level a .................................................................................. ... 39 figure 4-9: ddr video interface - 3g level b .................................................................................. .... 40 figure 4-10: delay adjustment ranges .......................................................................................... ........ 41 figure 4-11: switch line locking on a non-standard switch line ............................................... 42 figure 4-12: h:v:f output timing - 3g level a and hdtv 20-bit mode .................................... 46 figure 4-13: h:v:f output timing - 3g level a and hdtv 10-bit mode 3g level b 20-bit mode, each 10-bit stream .................................................................................... ..... 47 figure 4-14: h:v:f output timing - 3g level b 10-bit mode .......................................................... 47 figure 4-15: h:v:f output timing - hd 20-bit output mode ......................................................... 47 figure 4-16: h:v:f output timing - hd 10-bit output mode ......................................................... 47 figure 4-17: h:v:f output timing - sd 20-bit output mode .......................................................... 47 figure 4-18: h:v:f output timing - sd 10-bit output mode .......................................................... 47 figure 4-19: h:v:de output timing 1280 x 720p @ 59.94/60 (format 4) ................................... 49 figure 4-20: h:v:de output timing 1920 x 1080i @ 59.94/60 (format 5) ................................. 50 figure 4-21: h:v:de output timing 720 (1440) x 480i @ 59.94/60 (format 6&7) .................... 51 figure 4-22: h:v:de output timing 1280 x 720p @ 50 (format 19) ............................................. 51 figure 4-23: h:v:de output timing 1920 x 1080i @ 50 (format 20) ........................................... 52 figure 4-24: h:v:de output timing 720 (1440) x 576 @ 50 (format 21 & 22) ........................... 53 figure 4-25: h:v:de output timing 1920 x 1080p @ 59.94/60 (format 16) .............................. 53 figure 4-26: h:v:de output timing 1920 x 1080p @ 50 (format 31) .......................................... 54 figure 4-27: h:v:de output timing 1920 x 1080p @ 23.94/24 (format 32) .............................. 54 figure 4-28: h:v:de output timing 1920 x 1080p @ 25 (format 33) .......................................... 55 figure 4-29: h:v:de output timing 1920 x 1080p @ 29.97/30 (format 34) .............................. 55 figure 4-30: 2k feature enhancement ........................................................................................... ........ 59 figure 4-31: y/1anc and c/2anc signal timing .............. ................................................................ 66 figure 4-32: ancillary data extraction - step a ............................................................................... ... 73 figure 4-33: ancillary data extraction - step b ............................................................................... .... 74 figure 4-34: ancillary data extraction - step c ............................................................................... ... 74 figure 4-35: ancillary data extraction - step d ............................................................................... ... 75 figure 4-36: gspi application interface connection .......... .............................................................. 77 figure 4-37: command word format .............................................................................................. ....... 78 figure 4-38: data word format ................................................................................................. ............... 78 figure 4-39: write mode ....................................................................................................... ....................... 79 figure 4-40: read mode ........................................................................................................ ....................... 79 figure 4-41: gspi time delay .................................................................................................. .................. 79 figure 4-42: in-circuit jtag .................................................................................................. .................... 95 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 6 of 104 figure 4-43: system jtag ..................................... ................................................................. ..................... 96 figure 4-44: reset pulse ...................................................................................................... ......................... 97 figure 7-1: pb-free solder reflow profile ..................................................................................... ....... 103 list of tables table 1-1: pin descriptions .................................................................................................... ........................ 7 table 2-1: absolute maximum ratings........................... ................................................................. ....... 14 table 2-2: recommended operating conditions................................................................................ 14 table 2-3: dc electrical characteristics ....................................................................................... .......... 15 table 2-4: ac electrical characteristics ....................................................................................... .......... 17 table 4-1: serial digital output............................................................................................... .................. 29 table 4-2: pll loop bandwidth .................................................................................................. .............. 30 table 4-3: input clock requirements............................................................................................ .......... 31 table 4-4: lock detect conditions.............................................................................................. .............. 32 table 4-5: GS2961A output video data format selections .. .......................................................... 36 table 4-6: GS2961A pclk output rates ........................................................................................... ..... 38 table 4-7: switch line position for digital systems .......... ................................................................. 44 table 4-8: output signals available on programmabl e multi-function pins............................ 45 table 4-9: supported cea-861 formats........................................................................................... ...... 48 table 4-10: cea861 timing formats ....... ....................................................................................... ......... 49 table 4-11: supported video standard codes ..................................................................................... 56 table 4-12: data format register codes ......................................................................................... ....... 60 table 4-13: error status register and error mask register .............................................................. 63 table 4-14: smpte 352m packet data ............................................................................................. ....... 68 table 4-15: ioproc_disable register bits ....................................................................................... .. 70 table 4-16: gspi time delay.................................................................................................... .................. 79 table 4-17: gspi timing pa rameters (50% levels; 3.3v or 1.8v operation) ................................ 80 table 4-18: configuration and status registers................ ................................................................. .. 81 table 4-19: anc extraction fifo access re gisters............................................................................ 95 table 7-1: packaging data...................................................................................................... ................... 102 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 7 of 104 1. pin out 1.1 pin assignment 1.2 pin descriptions 13 2 45678910 a b c d e f g h j k pclk dvb_asi 20bit/ 10bit lf sdo standby rsv jtag/ host reset _trst a_vdd core _gnd sdo vbg sdi sdi buff_ vdd sdo_ en/dis lb_cont vco_ vdd vco_ gnd rsv pll_ vdd a_gnd a_gnd stat0 stat1 stat2 stat3 stat4 stat5 core _gnd core _gnd core _gnd core _vdd core _vdd core _vdd core _vdd dout1 dout0 dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dout10 dout11 dout14 dout13 dout16 dout15 dout18 dout17 dout19 dout12 io_vdd io_gnd pll_ vdd pll_ gnd pll_ vdd a_gnd a_gnd a_gnd rc_byp sw_en io_gnd io_vdd eq_vdd eq_gnd pll_ gnd pll_ gnd agcp rsv sdout_ tdo cs_ tms sdin_ tdi sclk_ tck smpte_ bypass io_gnd io_vdd tim_861 xtal_ out xtal2 xtal1 io_gnd io_vdd ioproc_ en/dis agcn a_gnd buff_ gnd core _gnd rsv rsv rsv rsv rsv rsv core _gnd table 1-1: pin descriptions pin number name timing ty p e description a1 vb g analo g input ban d g ap volta g e filter c onne c tion. a2 lf analo g input loop filter c omponent c onne c tion. a3 lb_ c ont analo g input c onne c tion for loop b an d wi d th c ontrol resistor. a4 v c o_vdd input power power pin for the v c o. c onne c t to a 1.2v5% analo g supply followe d b y a r c filter (see 5.3 typi c al appli c ation c ir c uit ). a 105 1% resistor must b e use d in the r c filter c ir c uit. v c o_vdd is nominally 0.7v. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 8 of 104 a5, a 6 , b5, b 6 , c 5, c6 s tat[0:5] output multi-fun c tional output port. please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. ea c h of the s tat [0:5] pins c an b e c onfi g ure d in d ivi d ually to output one of the followin g si g nals: s i g nal h/h s yn c v/v s yn c f/de lo c ked y/1an c c /2an c data error video error edh dete c ted c arrier dete c t rate_det0 rate_det1 default s tat0 s tat1 s tat2 s tat3 s tat4 ? s tat5 ? ? ? ? ? a7, d10, g 10, k7 io_vdd input power power c onne c tion for d i g ital i/o. c onne c t to 3.3v or 1.8v d c d i g ital. a8 p c lk output parallel data bu s c lo c k please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. 3 g 10- b it or 20- b it mo d ep c lk @ 148.5 or 148.5/1.001mhz hd 10- b it mo d ep c lk @ 148.5 or 148.5/1.001mhz hd 20- b it mo d ep c lk @ 74.25 or 74.25/1.001mhz s d 10- b it mo d ep c lk @ 27mhz s d 20- b it mo d ep c lk @ 13.5mhz (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 9 of 104 a9, a10, b8, b9, b10, c 8, c 9, c 10, e9, e10 dout18, 17, 19, 1 6 , 15, 12, 14, 13, 10, 11 output parallel data bu s please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. 20- b it mo d e 20 b it/10 b it = hi g h s mpte mo d e ( s mpte_bypa ss = hi g h an d dvb_a s i = low): luma d ata output for s d an d hd d ata rates; data s tream 1 for 3 g d ata rate dvb-a s i mo d e ( s mpte_bypa ss = low an d dvb_a s i = hi g h): not d efine d data-throu g h mo d e ( s mpte_bypa ss = low an d dvb_a s i = low): data output 10- b it mo d e 20 b it/10 b it = low s mpte mo d e ( s mpte_bypa ss = hi g h an d dvb_a s i = low): multiplexe d luma/ c hroma d ata output for s d an d hd d ata rates; multiplexe d data s tream 1&2 for 3 g d ata rate dvb-a s i mo d e ( s mpte_bypa ss = low an d dvb_a s i = hi g h): 8 b /10 b d e c o d e d dvb-a s i d ata data-throu g h mo d e ( s mpte_bypa ss = low an d dvb_a s i = low): data output b1 a_vdd input power power pin for analo g c ir c uitry. c onne c t to 3.3v d c analo g . b2, c 3, c 4 pll_vdd input power power pins for the re c lo c ker pll. c onne c t to 1.2v d c analo g . b3, f2, h4, j 3, j 4, j 5, k3, k4, k5 r s v these pins must b e left un c onne c te d . b4 v c o_ g nd input power g nd pin for the v c o. c onne c t to analo g g nd. b7, d9, g 9, j 7 io_ g nd input power g nd c onne c tion for d i g ital i/o. c onne c t to d i g ital g nd. c 1, d1 s di, s di analo g input s erial di g ital differential input. c 2, d2, d3, e3, f3, g 2 a_ g nd input power g nd pins for sensitive analo g c ir c uitry. c onne c t to analo g g nd. table 1-1: pin descriptions (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 10 of 104 c 7re s et_tr s t input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to reset the internal operatin g c on d itions to d efault settin g s an d to reset the j ta g sequen c e. normal mo d e ( j ta g /ho s t = low): when low, all fun c tional b lo c ks are set to d efault c on d itions an d all d i g ital output si g nals b e c ome hi g h impe d an c e. when hi g h, normal operation of the d evi c e resumes. j ta g test mo d e ( j ta g /ho s t = hi g h): when low, all fun c tional b lo c ks are set to d efault an d the j ta g test sequen c e is reset. when hi g h, normal operation of the j ta g test sequen c e resumes after re s et_tr s t is d e-asserte d . d4, e4, f4 pll_ g nd input power g nd pins for the re c lo c ker pll. c onne c t to analo g g nd. d5, e5, f5, g 4, g 5, h3 c ore_ g nd input power g nd c onne c tion for d evi c e c ore. c onne c t to d i g ital g nd. d 6 , e 6 , f 6 , g6 c ore_vdd input power power c onne c tion for d evi c e c ore. c onne c t to 1.2v d c d i g ital. d7 s w_en input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le swit c h-line lo c kin g , as d es c ri b e d in s e c tion 4.10.1 . d8 j ta g /ho s t input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t j ta g test mo d e or host interfa c e mo d e. when j ta g /ho s t is hi g h, the host interfa c e port is c onfi g ure d for j ta g test. when j ta g /ho s t is low, normal operation of the host interfa c e port resumes. e1 eq_vdd input power power pin for s di b uffer. c onne c t to 3.3v d c analo g . e2 eq_ g nd input power g nd pin for s di b uffer. c onne c t to analo g g nd. e7 s dout_tdo output c ommuni c ation s i g nal output please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. gs pi serial d ata output/test d ata out. in j ta g mo d e ( j ta g /ho s t = hi g h), this pin is use d to shift test results from the d evi c e. in host interfa c e mo d e, this pin is use d to rea d status an d c onfi g uration d ata from the d evi c e. note: gs pi is sli g htly d ifferent than the s pi. for more d etails on gs pi, please refer to 4.19 gs pi - ho s t interfa c e . table 1-1: pin descriptions (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 11 of 104 e8 s din_tdi input c ommuni c ation s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. gs pi serial d ata in/test d ata in. in j ta g mo d e ( j ta g /ho s t = hi g h), this pin is use d to shift test d ata into the d evi c e. in host interfa c e mo d e, this pin is use d to write a dd ress an d c onfi g uration d ata wor d s into the d evi c e. f1, g 1a gc p, a gc nautomati c g ain c ontrol for the equalizer. atta c h the a gc c apa c itor b etween these pins. f7 cs _tm s input c ommuni c ation s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. c hip sele c t / test mo d e start. in j ta g mo d e ( j ta g /ho s t = hi g h), this pin is test mo d e s tart, use d to c ontrol the operation of the j ta g test. in host interfa c e mo d e ( j ta g /ho s t = low), this pin operates as the host interfa c e c hip sele c t an d is a c tive low. f8 sc lk_t c k input c ommuni c ation s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. s erial d ata c lo c k si g nal. in j ta g mo d e ( j ta g /ho s t = hi g h), this pin is the j ta g c lo c k. in host interfa c e mo d e ( j ta g /ho s t = low), this pin is the host interfa c e serial b it c lo c k. all j ta g /host interfa c e a dd resses an d d ata are shifte d into/out of the d evi c e syn c hronously with this c lo c k. f9, f10, h9, h10, j 8, j 9, j 10, k8, k9, k10 dout8, 9, 6 , 7, 1, 4, 5, 0, 2, 3 output parallel data bu s please refer to the output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. 20- b it mo d e 20 b it/10 b it = hi g h s mpte mo d e ( s mpte_bypa ss = hi g h an d dvb_a s i = low): c hroma d ata output for s d an d hd d ata rates; data s tream 2 for 3 g d ata rate dvb-a s i mo d e ( s mpte_bypa ss = low an d dvb_a s i = hi g h): not d efine d data-throu g h mo d e ( s mpte_bypa ss = low an d dvb_a s i = low): data output 10- b it mo d e 20 b it/10 b it = low for c e d low table 1-1: pin descriptions (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 12 of 104 g 3r c _byp input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. when this pin is low, the serial d i g ital output is the b uffere d version of the input serial d ata. when this pin is hi g h, the serial d i g ital output is the re c lo c ke d version of the input serial d ata. g 7 s mpte_bypa ss input/output c ontrol s i g nal input/output please refer to the input/output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. in d i c ates the presen c e of vali d s mpte d ata. when the auto/man b it in the host interfa c e re g ister is hi g h (default), this pin is an output. s mpte_bypa ss is hi g h when the d evi c e lo c ks to a s mpte c ompliant input. s mpte_bypa ss is low un d er all other c on d itions. when the auto/man b it in the host interfa c e re g ister is low, this pin is an input: no s mpte s c ram b lin g takes pla c e, an d none of the i/o pro c essin g features of the d evi c e are availa b le when s mpte_bypa ss is set low. when s mpte_bypa ss is set hi g h, the d evi c e c arries out s mpte s c ram b lin g an d i/o pro c essin g . when s mpte_bypa ss an d dvb_a s i are b oth set low, the d evi c e operates in data-throu g h mo d e. g 8dvb_a s i input/output c ontrol s i g nal input please refer to the input/output lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le/ d isa b le dvb-a s i d ata extra c tion in manual mo d e. when the auto/man b it in the host interfa c e is low, this pin is an input an d when the dvb_a s i pin is set hi g h the d evi c e will c arry out dvb_a s i d ata extra c tion an d pro c essin g . the s mpte_bypa ss pin must b e set low. when s mpte_bypa ss an d dvb_a s i are b oth set low, the d evi c e operates in data-throu g h mo d e. when the auto/man b it in the host interfa c e is hi g h ( d efault), dvb-a s i is c onfi g ure d as a status output (set low), an d dvb-a s i input streams are not supporte d or re c o g nize d . h1 buff_vdd input power power pin for the serial d i g ital output 50 b uffer. c onne c t to 3.3v d c analo g . h2 buff_ g nd input power g nd pin for the c a b le d river b uffer. c onne c t to analo g g nd. h5 tim_8 6 1 input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t c ea-8 6 1 timin g mo d e. when tim_8 6 1 is hi g h, the d evi c e outputs c ea 8 6 1 timin g si g nals (h s yn c /v s yn c /de) instea d of h:v:f d i g ital timin g si g nals. h 6 xtal_out di g ital output buffere d 27mhz c rystal output. c an b e use d to c as c a d e the c rystal si g nal. table 1-1: pin descriptions (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 13 of 104 h7 20 b it/10 b it input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to sele c t the output b us wi d th. hi g h = 20- b it, low = 10- b it. h8 iopro c _en/di s input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le or d isa b le vi d eo pro c essin g features. when iopro c _en is hi g h, the vi d eo pro c essin g features of the d evi c e are ena b le d . when iopro c _en is low, the pro c essin g features of the d evi c e are d isa b le d , an d the d evi c e is in a low-laten c y operatin g mo d e. j 1, k1 s do, s do output s erial data output s i g nal. 50 c ml b uffer for interfa c in g to an external c a b le d river. s erial d i g ital output si g nal operatin g at 2.97 gb /s, 2.97/1.001 gb /s, 1.485 gb /s, 1.485/1.001 gb /s an d 270m b /s. j 2 s do_en/di s input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. use d to ena b le/ d isa b le the serial d i g ital output sta g e. when s do_en/di s is low, the serial d i g ital output si g nals, s do an d s do , are b oth pulle d hi g h. when s do_en/di s is hi g h, the serial d i g ital output si g nals, s do an d s do , are ena b le d . j6 , k 6 xtal2, xtal1 analo g input input c onne c tion for 27mhz c rystal. k2 s tandby input c ontrol s i g nal input please refer to the input lo g i c parameters in the d c ele c tri c al c hara c teristi c s ta b le for lo g i c level threshol d an d c ompati b ility. when this pin is set hi g h, the d evi c e is pla c e d in a power-savin g mo d e. no d ata pro c essin g o cc urs, an d the d i g ital i/os are powere d d own. in this mo d e, the serial d i g ital output si g nals, s do an d s do , are b oth pulle d hi g h. table 1-1: pin descriptions (continued) pin number name timing ty p e description GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 14 of 104 2. electrical characteristics 2.1 absolute maximum ratings 2.2 recommended operating conditions table 2-1: absolute maximum ratings parameter value/units s upply volta g e, di g ital c ore ( c ore_vdd) -0.3v to +1.5v s upply volta g e, di g ital i/o (io_vdd) -0.3v to +4.0v s upply volta g e, analo g 1.2v (pd_vdd, v c o_vdd) -0.3v to +1.5v s upply volta g e, analo g 3.3v (eq_vdd, buff_vdd, a_vdd) -0.3v to +4.0v input volta g e ran g e ( d i g ital inputs) -2.0v to +5.25v operatin g temperature ran g e -20 c to +85 c fun c tional temperature ran g e -40 c to +85 c s tora g e temperature ran g e -50 c to +125 c peak reflow temperature ( j ede c j - s td-020 c )2 6 0 c e s d s ensitivity, hbm ( j e s d22-a114) 2kv note s : a b solute maximum ratin g s are those values b eyon d whi c h d ama g e may o cc ur. fun c tional operation un d er these c on d itions or at any other c on d ition b eyon d those in d i c ate d in the a c /d c ele c tri c al c hara c teristi c s se c tions is not implie d . table 2-2: recommended operating conditions t a = -20 c to + 85 c , unless otherwise shown. parameter symbol conditions min ty p max units notes s upply volta g e, di g ital c ore c ore_vdd ? 1.14 1.2 1.2 6 v? s upply volta g e, di g ital i/o io_vdd 1.8v mo d e 1.71 1.8 1.89 v ? 3.3v mo d e 3.13 3.3 3.47 v ? s upply volta g e, pll pll_vdd ? 1.14 1.2 1.2 6 v? s upply volta g e, analo g a_vdd ? 3.13 3.3 3.47 v 1 s upply volta g e, s erial di g ital input eq_vdd ? 3.13 3.3 3.47 v 1 s upply volta g e, c d buffer buff_vdd ? 3.13 3.3 3.47 v 1 notes: 1. the 3.3v supplies must track th e 3.3v supply of an external cd. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 15 of 104 2.3 dc electrical characteristics table 2-3: dc electrical characteristics g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes system +1.2v s upply c urrent i 1v2 10 b it 3 g ? 200 240 ma ? 20 b it 3 g ? 190 240 ma ? 10/20 b it hd ? 1 6 0 200 ma ? 10/20 b it s d ? 130 170 ma ? dvb_a s i ? 130 170 ma ? +1.8v s upply c urrent i 1v8 10 b it 3 g ? 37 45 ma ? 20 b it 3 g ? 1 6 20 ma ? 10/20 b it hd ? 15 21 ma ? 10/20 b it s d ? 47ma ? dvb_a s i ? 4 6 ma ? +3.3v s upply c urrent i 3v3 10 b it 3 g ? 150 180 ma ? 20 b it 3 g ? 115 130 ma ? 10/20 b it hd ? 110 135 ma ? 10/20 b it s d ? 90 100 ma ? dvb_a s i ? 90 95 ma ? total devi c e power (io_vdd = 1.8v) p 1d8 10 b it 3 g ? 540 6 40 mw ? 20 b it 3 g ? 500 6 00 mw ? 10/20 b it hd ? 4 6 05 6 0mw ? 10/20 b it s d ? 410 490 mw ? dvb_a s i ? 410 490 mw ? reset ? 390 ? mw ? s tan db y ? 23 45 mw ? total devi c e power (io_vdd = 3.3v) p 3d3 10 b it 3 g ? 720 890 mw ? 20 b it 3 g ? 6 00 720 mw ? 10/20 b it hd ? 550 700 mw ? 10/20 b it s d ? 440 540 mw ? dvb_a s i ? 440 530 mw ? reset ? 410 ? mw ? s tan db y ? 23 45 mw ? digital i/o input lo g i c low v il 3.3v or 1.8v operation io_v ss -0.3 ? 0.3 x io_vdd v? input lo g i c hi g h v ih 3.3v or 1.8v operation 0.7 x io_vdd ? io_vdd +0.3 v? GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 16 of 104 output lo g i c low v ol iol = 5ma, 1.8v operation ? ? 0.2 v ? iol = 8ma, 3.3v operation ? ? 0.4 v ? output lo g i c hi g h v oh ioh = 5ma, 1.8v operation 1.4 ? ? v ? ioh = 8ma, 3.3v operation 2.4 ? ? v ? serial input s erial input c ommon mo d e volta g e ?75 loa d ?2.2?v? serial output s erial output c ommon mo d e volta g e ? 50 loa d buff_vdd -(0. 6 /2) buff_vdd -(0.45/2) buff_vdd -(0.35/2) v ? notes: the output drive strength of the digi tal outputs can be programmed thr ough the host interface. please see table 4-18: configuration and status registers , register 06dh for details. table 2-3: dc electrical characteristics (continued) g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 17 of 104 2.4 ac electrical characteristics table 2-4: ac electrical characteristics g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes system devi c e laten c y: s mpte mo d e, iopro c _en = 1 ? 3 g (level a) 44 ? 48 p c lk ? 3 g (level b) 108 ? 11 6 p c lk ? hd 44 ? 48 p c lk ? s d44?48p c lk ? devi c e laten c y: s mpte mo d e, iopro c _en = 0 ? 3 g (level a) 33 ? 3 6 p c lk ? hd 33 ? 3 6 p c lk ? s d32?35p c lk ? devi c e laten c y: s mpte b ypass, iopro c _en = 0 ? 3 g (level a) 6 ?9p c lk ? hd 6 ?9p c lk ? s d5?9p c lk ? devi c e laten c y: dvb-a s i ? s d12?1 6 p c lk ? reset pulse wi d th t reset ?1??ms? parallel output parallel c lo c k frequen c yf p c lk ? 13.5 ? 148.5 mhz ? parallel c lo c k duty c y c le d c p c lk ?40? 6 0% ? GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 18 of 104 output data hol d time (1.8v) t oh 3 g 10- b it 6 pf c loa d s pi 1.5 ? ? ns 1 dbu s 0.3 ? ? ns 1 s tat 0.3 ? ? ns 1 3 g 20- b it 6 pf c loa d dbu s 1.0 ? ? ns 1 s tat 1.0 ? ? ns 1 hd 10- b it 6 pf c loa d dbu s 1.0 ? ? ns 1 s tat 1.0 ? ? ns 1 hd 20- b it 6 pf c loa d dbu s 1.0 ? ? ns 1 s tat 1.0 ? ? ns 1 s d 10- b it 6 pf c loa d dbu s 19.4 ? ? ns 1 s tat 19.4 ? ? ns 1 s d 20- b it 6 pf c loa d dbu s 38.0 ? ? ns 1 s tat 38.0 ? ? ns 1 output data hol d time (3.3v) t oh 3 g 10- b it 6 pf c loa d s pi 1.5 ? ? ns 2 dbu s 0.3 ? ? ns 2 s tat 0.3 ? ? ns 2 3 g 20- b it 6 pf c loa d dbu s 1.0 ? ? ns 2 s tat 1.0 ? ? ns 2 hd 10- b it 6 pf c loa d dbu s 1.0 ? ? ns 2 s tat 1.0 ? ? ns 2 hd 20- b it 6 pf c loa d dbu s 1.0 ? ? ns 2 s tat 1.0 ? ? ns 2 s d 10- b it 6 pf c loa d dbu s 19.4 ? ? ns 2 s tat 19.4 ? ? ns 2 s d 20- b it 6 pf c loa d dbu s 38.0 ? ? ns 2 s tat 38.0 ? ? ns 2 table 2-4: ac electrical characteristics (continued) g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 19 of 104 output data delay time (1.8v) t o d 3 g 10- b it 15pf c loa d s pi ? ? 14.0 ns 3 dbu s ??1.8ns 3 s tat ? ? 2.5 ns 3 3 g 20- b it 15pf c loa d dbu s ??3.7ns 3 s tat ? ? 4.4 ns 3 hd 10- b it 15pf c loa d dbu s ??3.7ns 3 s tat ? ? 4.4 ns 3 hd 20- b it 15pf c loa d dbu s ??3.7ns 3 s tat ? ? 4.4 ns 3 s d 10- b it 15pf c loa d dbu s ? ? 22.2 ns 3 s tat ? ? 22.2 ns 3 s d 20- b it 15pf c loa d dbu s ? ? 41.0 ns 3 s tat ? ? 41.0 ns 3 output data delay time (3.3v) t o d 3 g 10- b it 15pf c loa d s pi ? ? 14.0 ns 4 dbu s ??1.9ns 4 s tat ? ? 2.2 ns 4 3 g 20- b it 15pf c loa d dbu s ??3.7ns 4 s tat ? ? 4.1 ns 4 hd 10- b it 15pf c loa d dbu s ??3.7ns 4 s tat ? ? 4.1 ns 4 hd 20- b it 15pf c loa d dbu s ??3.7ns 4 s tat ? ? 4.1 ns 4 s d 10- b it 15pf c loa d dbu s ? ? 22.2 ns 4 s tat ? ? 22.2 ns 4 s d 20- b it 15pf c loa d dbu s ? ? 41.0 ns 4 s tat ? ? 41.0 ns 4 table 2-4: ac electrical characteristics (continued) g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 20 of 104 output data rise/fall time (1.8v) t r /t f 3 g 10- b it 6 pf c loa d s tat ? ? 0.4 ns 1 dbu s ??0.3ns 1 all other mo d es 6 pf c loa d s tat ? ? 0.4 ns 1 dbu s ??0.4ns 1 3 g 10- b it 15pf c loa d s tat ? ? 1.5 ns 3 dbu s ??1.1ns 3 all other mo d es 15pf c loa d s tat ? ? 1.5 ns 3 dbu s ??1.4ns 3 output data rise/fall time (3.3v) t r /t f 3 g 10- b it 6 pf c loa d s tat ? ? 0.5 ns 2 dbu s ??0.4ns 2 all other mo d es 6 pf c loa d s tat ? ? 0.5 ns 2 dbu s ??0.4ns 2 output data rise/fall time (3.3v) t r /t f 3 g 10- b it 15pf c loa d s tat ? ? 1. 6 ns 4 dbu s ??1.5ns 4 all other mo d es 15pf c loa d s tat ? ? 1. 6 ns 4 dbu s ??1.4ns 4 serial digital input s erial input data rate dr s di ? 0.27 ? 2.97 gb /s ? s erial input volta g e s win g v s di t a =25 c , d ifferential, 270m b /s & 1.485 gb /s 720 800 950 mv p-p 6 t a =25 c , d ifferential, 2.97 gb /s 720 800 880 mv p-p 6 a c hieva b le c a b le len g th ?bel d en 1 6 94a c a b le, 3 g ?150 ? m ? bel d en 1 6 94a c a b le, hd ? 230 ? m ? bel d en 1 6 94a c a b le, s d? 440 ? m ? input return loss ? s in g le-en d e d 15 21 ? d b7 input resistan c e? s in g le-en d e d ?1.52 ? k ? input c apa c itan c e? s in g le-en d e d ?1 ? pf ? serial digital output s erial output data rate dr s do ? 0.27 ? 2.97 gb /s ? s erial output s win g v sdo differential with 100 loa d 320 ? 6 00 mvp-p ? s erial output rise time 20% ~ 80% tr s do ? ? ? 180 ps ? table 2-4: ac electrical characteristics (continued) g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 21 of 104 s erial output fall time 20% ~ 80% tf s do ? ? ? 180 ps ? s erial output j itter with loop-throu g h mo d e t o j s mpte c olour b ar 3 g , 150m ? ? 100 ps ? s mpte c olour b ar hd, 250m ? ? 100 ps ? s mpte c olour b ar s d, 480m ? ? 470 ps ? s erial output duty c y c le distortion d c d s dd 3 g ?10 ? ps ? hd ? 10 ? ps ? s d?20?ps? s yn c hronous lo c k time ? ? ? ? 25 s? asyn c hronous lo c k time ? ? 0.1 ? 20 ms ? lo c k time from power-up ? after 20 minutes at -20 c ?? 5 s ? gspi gs pi input c lo c k frequen c yf sc lk 50% levels 3.3v or 1.8v operation ?? 6 0mhz 5 gs pi input c lo c k duty c y c le d c sc lk 40 50 6 0% 5 gs pi input data s etup time ? 1.5 ? ? ns 5 gs pi input data hol d time ? 1.5 ? ? ns 5 gs pi output data hol d time ? 1.5 ? ? ns 5 cs low b efore sc lk risin g e dg e? 1.5??ns5 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - write c y c le ? 37.1 ? ? ns 5 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g d ata wor d - rea d c y c le ? 148.4 ? ? ns 5 cs hi g h after sc lk fallin g e dg e ? 50% levels 3.3v or 1.8v operation 37.1 ? ? ns 5 notes: 1. 1.89v and 0oc. 2. 3.47v and 0oc. 3. 1.71v and 85oc 4. 3.13v and 85oc 5. timing parameters defined in section 4.19.3 6. 0m cable length 7. tested on a GS2961A board from 5mhz to 3ghz table 2-4: ac electrical characteristics (continued) g uarantee d over re c ommen d e d operatin g c on d itions unless otherwise note d . parameter symbol conditions min ty p max units notes GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 22 of 104 3. input/output circuits fi g ure 3-1:di g ital input pin with sc hmitt tri gg er (20 b it/ 10 b it , cs _tm s , s w_en, iopro c _en/ di s , j ta g / ho s t , r c _byp , re s et_tr s t , sc lk_t c k, s din_tdi, s do_en/ di s , s tandby, tim_8 6 1) fi g ure 3-2:bi d ire c tional di g ital input/output pin - c onfi g ure d to output unless in reset mo d e. (dvb_a s i, s mpte_bypa ss ) io_vdd 200 input pin io_vdd 200 output pin GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 23 of 104 fi g ure 3-3:bi d ire c tional di g ital input/output pin with pro g ramma b le d rive stren g th. these pins are c onfi g ure d to output unless in reset mo d e; in whi c h c ase they are hi g h-impe d an c e. the d rive stren g th c an b e set b y writin g to a dd ress 0 6 dh in the host interfa c e re g ister. (dout0, dout1, dout2, dout3, dout4, dout5, dout 6 , dout7, dout8, dout9, s dout_tdo, s tat0, s tat1, s tat2, s tat3, s tat4, s tat5, xtal_out, dout10, dout11, dout12, dout13, dout14, dout15, dout1 6 , dout17, dout18, dout19, p c lk) fi g ure 3-4:xtal1/xtal2/xtal-out io_vdd 200 output pin xtal1 xtal2 xtal_out GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 24 of 104 fi g ure 3-5:vb g fi g ure 3- 6 :lb_ c ont fi g ure 3-7:loop filter vbg 50 2k a_vdd out <0> out <1> eq_vdd lb_cont 25 pll_vdd lf 25 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 25 of 104 fi g ure 3-8: s do/ s do fi g ure 3-9:equalizer input equivalent c ir c uit 50 50 sdo sdo buff_vdd 4k 6k 4k 6k rc sdi sdi GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 26 of 104 4. detailed description 4.1 functional overview the GS2961A is a multi-rate sd i integrated receiver whic h includes complete smpte processing, as per smpte 425m, 292m and smpte 259m-c. the smpte processing features can be bypassed to support signals with other coding schemes. the GS2961A integrates gennu m's adaptive cable equalizer tech nology, achieving unprecedented cable lengths and jitter tolerance. it features dc restoration to compensate for the dc content of smpte pathological signals. the device features an integrated reclocker with an internal vco and a wide input jitter tolerance (ijt) of 0.7ui. a serial digital loop through output is provided, which can be configured to output either reclocked or non-reclocked serial digital data. the serial digital output can be connected to an external cable driver. the device operates in one of four basic modes: smpte mode, dvb-asi mode, data-through mode or standby mode. in smpte mode, the GS2961A performs sm pte de-scrambling and nrzi to nrz decoding and word alignment. line-based crc errors, line number errors, trs errors and ancillary data ch eck sum errors can all be dete cted. the GS2961A also provides ancillary data extraction. the entire ancillary data packet is extracted, and written to host-accessible registers. other processing functions include h:v:f timing extraction, luma and chroma ancillary da ta indication, video standard detection, and smpte 352m packet detection and decoding. all of the processing features are optional, and may be enabled or disabled via the host interface. both smpte 425m level a and le vel b inputs are supported. the GS2961A also provides user-selectable conversion fr om level b to leve l a for 1080p 50/60 4:2:2 10-bit formats only. in dvb-asi mode, 8b/10b decoding is applied to the received data stream. in data-through mode, all forms of smpte and dvb-asi decoding are disabled, and the device can be used as a simple serial to parallel converter. the device can also be placed in a lower power standby mode. in this mode, no signal processing is carried out and the parallel output is held static. placing the receiver in standby mode will automatically place the integrated equalizer in power down mode as well. parallel data outputs are provided in 20-bit or 10-bit multiplexed format for 3gb/s, hd and sd video rates. for 1080p 50/60 4:2:2 10-bit, the para llel data is output on the 20-bit parallel bus as y on 10 bits and cb/cr on the other 10 bits. as such, this parallel bus can interface directly with video processor ics. for other smpte 425m mapping structures, the video data is mapped to a 20-bit virtual interface as described in smpte 425m. in all cases this 20-bit parallel bus can be multiplexed onto 10 bits for a low pin count interface with downstream device s. the associated parallel clock input signal operates at 148.5 or 148.5/1.001mhz (for all 3gb/s hd 10-bit multiplexed modes), 74.25 or 74.25/1.001mhz (for hd 20-bit mode), 27mhz (f or sd 10-bit mode) and 13.5mhz (for sd 20-bit mode). GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 27 of 104 note: for 3gb/s 10-bit mode the device operates in dual data rate (ddr) mode, where the data is sampled at both the rising and fa lling edges of the clock. this reduces the i/o speed requirements of the downstream devices. 4.2 smpte 425m mapping - 3g level a and level b formats 4.2.1 level a mapping direct image format mapping - the mapping structure used to define 1080p/50/59.94/60 4:2:2 ycbcr 10 bit data, as su pported by the GS2961A. see figure 4-1 : fi g ure 4-1:level a mappin g 4.2.2 level b mapping the 2 x 292 hd sdi interface - this can be tw o distinct links running at 1.5gb/s or one 3gb/s link formatted according to smpte 292 on two 10-bit links (y /c interleaved). for 1080p/50/59.94/60 4:2:2 video formats, each link should be line -interleaved as per smpte 372m. see figure 4-2 : fi g ure 4-2:level b mappin g the GS2961A distinguishes be tween level a and level b mappings at 3gb/s. when level b data is detected, each 10-bit link is demultiplexed into its individual component streams, and most video processing featur es, including error detection and correction are enabled separately for data stream 1 and data stream 2 (link a and link b, respectively). note that ancillary data extraction can only be enabled for one link for 3gb/s level b data. data stream 1 or data stream 2 can be selected via the host interface. data stream 1 data stream 2 3ff 000 000 xyz ln0 ln1 crc0 crc1 3ff 000 000 xyz 3ff 000 000 xyz ln0 ln1 crc0 crc1 audio data audio data audio data audio data audio data audio data audio data audio data audio data audio data audio data audio data canc data canc data canc data canc data hblank hblank hblank hblank 3ff 000 000 xyz y0 y1 cb0 y2 y3 y4 y5 y6 y7 y8 y9 cb1 cb2 cb3 cb4 cb5 cb6 cb7 cb8 cb9 cb10 cb11 cb12 cb13 cb14 cb15 eav hanc sav active video hblank hblank hblank hblank hblank hblank hblank hblank cb16 cb17 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23 y24 y25 y26 y27 y28 y29 y30 y31 y32 y33 y34 y35 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 cr16 cr17 yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data yanc data audio ctl audio ctl audio ctl audio ctl data stream 1 (?link a?) data stream 2 (?link 2?) 3ff 000 000 xyz ln0 ln1 crc0 crc1 000 000 xyz eav hanc sav active video 3ff 3ff 000 000 xyz crc1 crc0 ln1 ln0 xyz 000 000 3ff 3ff 000 000 xyz ln0 ln1 crc0 crc1 crc1 crc0 ln1 ln0 xyz 000 000 3ff 000 000 xyz 3ff 3ff 000 000 xyz ?double? trs headers from interleaved hd-sdi; multiplexed y/c data cb[1] 0 y[1] 0 cr[1] 0 y[1] 1 y[1] 2 y[1] 3 y[1] 4 y[1] 5 y[1] 6 y[1] 7 y[1] 8 y[1] 9 y[1] 10 y[1] 11 y[1] 12 y[1] 13 y[1] 14 y[1] 15 y[1] 16 y[1] 17 cr[1] 1 cr[1] 2 cr[1] 3 cr[1] 4 cr[1] 5 cr[1] 6 cr[1] 7 cr[1] 8 cb[1] 1 cb[1] 2 cb[1] 3 cb[1] 4 cb[1] 5 cb[1] 6 cb[1] 7 cb[1] 8 audio ctl[1] cb[2] 0 y[2] 0 cr[2] 0 y[2] 1 y[2] 2 y[2] 3 y[2] 4 y[2] 5 y[2] 6 y[2] 7 y[2] 8 y[2] 9 y[2] 10 y[2] 11 y[2] 12 y[2] 13 y[2] 14 y[2] 15 y[2] 16 y[2] 17 cr[2] 1 cr[2] 2 cr[2] 3 cr[2] 4 cr[2] 5 cr[2] 6 cr[2] 7 cr[2] 8 cb[2] 1 cb[2] 2 cb[2] 3 cb[2] 4 cb[2] 5 cb[2] 6 cb[2] 7 cb[2] 8 audio ctl[2] audio data[2] audio ctl[1] audio ctl[1] audio ctl[1] yanc data[2] yanc data[1] yanc data[1] yanc data[1] yanc data[1] audio data[1] audio data[1] audio data[1] audio data[1] audio data[1] audio data[1] audio data[1] audio data[1] audio data[2] audio data[2] audio data[2] audio data[2] audio data[2] audio data[2] audio data[2] audio ctl[2] audio ctl[2] audio ctl[2] yanc data[2] yanc data[2] yanc data[2] GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 28 of 104 4.3 serial digital input the GS2961A can accept serial digital inputs comp liant with smpte 424m, smpte 292 and smpte 259m-c. 4.3.1 integrated adaptive cable equalizer the GS2961A integrates ge nnum's adaptive cable equalizer technology. the integrated adaptive equalizer can equalize 3gb/s, hd and sd se rial digital signals, and will typically equalize 150m of belden 1694a cable at 2.97gb/s, 250m at 1. 485gb/ s and 480m at 270mb/s.the integr ated adaptive equalizer is powered from a single +3.3v power supply and consumes approximately 195mw of power. the equalizer can be bypassed by programming register 073h through the gspi interface. 4.3.1.1 serial digital inputs the serial data signal may be connected to the input pins (sdi/sdi ) in either a differential or single ended configuration. ac coupling of the inputs is recommended, as the sdi and sdi inputs are internally biased at approximately 1.8v. 4.3.1.2 cable equalization the input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. in addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by both an internal and an external agc filter capacitor providing a st eady control voltage fo r the gain stage. as the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is also dc restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to ac coupling. fi g ure 4-3: gs 29 6 1a inte g rate d eq blo c k dia g ram e q ualizer output agc sdi sdo sdi sdo agc agc gain_sel dc restore GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 29 of 104 4.4 serial digital loop-through output the GS2961A contains a 100 differential serial output bu ffer which can be configured to output either a retimed or a buffered version of the serial digital input. the sdo and sdo outputs of this buffer can interface directly to a 3gb/s-capable, smpte compliant gennum cable driver. see 5.3 typical appl ication circuit on page 99 . when the rc_byp pin is set high, the serial digital output is the re-timed version of the serial input. when the rc_byp pin is set low, the serial digital output is simply the buffered version of the serial input, bypassing the internal reclocker. the output can be disabled by setting the sdo_en/dis pin low. the output is also disabled when the standby pin is asserted high. when the output is disabled, both sdo and sdo pins are set to vdd and remain static. the sdo output is muted when the rc_byp pin is set high and the pll is unlocked (locked pin is low). when muted, the output is held static at logic ?0? or logic ?1?. note : the serial digital output is mu ted when the GS2961A is unlocked. 4.5 serial digital reclocker the GS2961A includes both a p ll stage and a sampling stage. the pll is comprised of two distinct loops: ? a coarse frequency acquisition loop sets the centre frequency of the integrated voltage controlled oscillator (vco) usin g an external 27mhz reference clock ? a fine frequency and phase locked loop aligns the vco?s phase and frequency to the input serial digital stream the frequency lock loop result s in a very fast lock time. the sampling stage re-times the serial digital input with the locked vco clock. this generates a clean serial di gital stream, which may be output on the sdo/sdo output pins and converted to parallel data for further processing. parallel data is not affected by rc_byp . only the sdo is affected by this pin. table 4-1: serial digital output sdo_en/dis rc_byp sdo/sdo 0x disa b le d 11 re-time d 10buffere d (not re-time d ) GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 30 of 104 4.5.1 pll loop bandwidth the fine frequency and phase lock loop in the GS2961A reclocker is non-linear. the pll loop bandwidth scales with the jitter amplit ude of the input data stream; automatically reduces bandwidth in response to higher jitter. this allows the pll to reject more of the jitter in the input data stream and produce a very clean reclocked output. the loop bandwidth of the GS2961A pll is defined with 0.2ui input jitter. the bandwidth is controlled by the lb_cont pin. under nominal conditions, with the lb_cont pin floating and 0.2ui input jitter applied, the loop band width is set to 1/1000 of the frequency of the input data stream. connecting the lb_cont pin to 3.3v reduces the bandwidth to half of the nominal setting. connecting the lb_cont pin to gnd increases the bandwidth to double the nominal setting. table 4-2 below summarizes this information. 4.6 external crysta l/reference clock the GS2961A requires an extern al 27mhz reference clock fo r correct operation. this reference clock is generated by connecting a crystal to the xtal1 and xtal2 pins of the device. see application reference design on page 98 . table 4-3 shows xtal characteristics. alternately, a 27mhz external clock source can be connected to the xtal1 pin of the device, as shown in figure 4-4 . the frequency variation of the crystal including aging, supply and temperature variation, should be less than +/-100ppm. the equivalent series resistance (or motion al resistance) should be a maximum of 50 . the external crystal is used in the frequency acquisition process. it has no impact on the output jitter performance of the part when the part is locked to incoming data. because of this, the only key parameter is the frequency variation of the crystal that is stated above. table 4-2: pll loop bandwidth input data rate lb_cont pin connection loop bandwidth (mhz) 1 s d 3.3v 0.135 floatin g 0.27 0v 0.54 hd 3.3v 0.75 floatin g 1.5 0v 3.0 3 g 3.3v 1.5 floatin g 3.0 0v 6 .0 1 measure d with 0.2ui input jitter applie d GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 31 of 104 fi g ure 4-4:27mhz c lo c k s our c es external crystal connection xtal1 xtal2 xtal1 xtal2 external clock source connection 16pf 16pf external clock nc k6 k6 j6 j6 notes: 1. capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2.xtal1 serves as an input, which may alternatively accept a 27mhz clock source. table 4-3: input clock requirements parameter min ty p max uom notes xtal1 low level input volta g e (v il ) ?? 20% of vdd_io v 3 xtal1 hi g h level input volta g e (v ih ) 80% of vddio ?? v3 xtal1 input s lew rate 2 ?? v/ns 3 xtal1 to xout prop. delay (hi g h to low) 1.3 1.5 2.3 ns 3 xtal1 to xout prop. delay (low to hi g h) 1.3 1. 6 2.3 ns 3 note s : vali d when the c ell is use d to b uffer an external c lo c k sour c e whi c h is c onne c te d to the xtal1 pin, then nothin g shoul d b e c onne c te d to the xtal2 pin. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 32 of 104 4.7 lock detect the locked output signal is available by default on the stat3 output pin, but may be programmed to be output through any one of the six programmable multi-functional pins of the device; stat[5:0]. the locked output signal is set high by the lock detect block under the following conditions: note 1: the part will lock to asi auto mode, but could falsely unlock for some asi input patterns. note 2: in standby mode, the reclocker pll un locks. however, the locked signal retains whatever state it previously held. so , if before standby assertion, the locked signal is high, then during standby, it rema ins high regardless of the status of the pll. 4.7.1 asynchronous lock the lock detection algorithm is a continuous process, beginning at device power-up or after a system reset. it continues until the device is powered down or held in reset. the device first determines if a valid serial digital input signal has been presented to the device. if no valid serial data stream has been detected, the serial data into the device is considered invalid, and the locked signal is low. once a valid input signal has been detected, the asynchronous lock algorithm enters a ?hunt? phase, in which the device attempts to detect the presence of either trs words or dvb-asi sync words. by default, the device powers up in auto mode (the auto/man bit in the host interface is set high). in this mode, the device operating frequency toggles between 3g, hd and sd rates as it attempts to lock to the incoming data rate. the pclk output continues to operate, and the frequency may switch between 148.5mhz, 74.25mhz, 27mhz and 13.5mhz. table 4-4: lock detect conditions mode of operation mode setting condition for locked data-throu g h mo d e s mpte_bypa ss = low dvb_a s i = low re c lo c ker pll is lo c ke d . s mpte mo d e s mpte_bypa ss = hi g h dvb_a s i = low re c lo c ker pll is lo c ke d . three c onse c utive tr s wor d s are d ete c te d in a two-line win d ow. s mpte mo d e with lo c k noise-immunity ena b le d s mpte_bypa ss = hi g h dvb_a s i = low bit 0x085[10] set to 1 auto/man = hi g h re c lo c ker pll is lo c ke d . two c onse c utive tr s wor d s are d ete c te d in a two-line win d ow. the last two d ete c te d tr s wor d s must have the same ali g nment. note: auto mo d e only. not supporte d in manual mo d e. dvb_a s i mo d e s mpte_bypa ss = low dvb_a s i = hi g h bit auto/man = low re c lo c ker pll is lo c ke d . 32 c onse c utive dvb_a s i wor d s with no errors are d ete c te d within a 128-wor d win d ow. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 33 of 104 when the device is operatin g in manual mode (auto/man bit in the host interface is low), the operating frequency needs to be set through the host interface using the rate_det[1:0] bits. in this mode, the asynchronous lock algorithm does not toggle the operating rate of the device and attempts to lock within a single standard. lock is achieved within three lines of the selected standard. 4.7.2 signal interruption the device tolerates a signal interruption of up to 10 s without unlocking, as long as no trs words are deleted by this interruption. if a signal interruption of greater than 10 s is detected, the lock detection algorithm may lose the current data rate, and locked will de-assert until the data rate is re-acquired by the lock detection block. 4.8 smpte functionality 4.8.1 descrambling an d word alignment the GS2961A performs nrzi to nrz decoding and data de scrambling according to smpte 424m/smpte 292/smpte 259m -c and word aligns the data to trs sync words. when operating in manual mode (auto/man = low), the device only carries out smpte decoding, descrambling and word alignment when the smpte_bypass pin is set high and the dvb_asi pin is set low. when operating in auto mode (auto/man = high), the GS2961A carries out descrambling and word alignment to enable the detection of trs sync words. when two consecutive valid trs words (sav and eav), with the same bit alignment have been detected, the device word-aligns the data to the trs id words. trs id word detection is a continuous proces s. the device remains in smpte mode until trs id words fail to be detected. note 1: both 8-bit and 10-bit trs header s are identified by the device. note 2: in 3g level b mode, the device only su pports data stream 1 and data stream 2 having the same bit width (i.e. both data streams contain 8-bit data, or both data streams contain 10-bit data). if the bit widths between the two data streams are different, the GS2961A cannot word align the input stre am, and switches in data-through mode. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 34 of 104 4.9 parallel data outputs the parallel data outputs are aligned to the rising edge of the pclk. 4.9.1 parallel data bus buffers the parallel data bus, status signal outp uts and control signal input pins are all connected to high-impedance buffers. the device supports 1.8 or 3.3v (lvttl an d lvcmos levels) supplied at the io_vdd and io_gnd pins. all output buffers (including the pclk output), are set to high-impedance in reset mode (reset_trst = low). fi g ure 4-5:p c lk to data an d c ontrol s i g nal output timin g - s dr mo d e 1 toh tr/tf (min) cload tod tr/tf (max) cload toh tr/tf (min) cload tod tr/tf (max) cload dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns 10bhd mode 3.3v 1.8v 6 pf 15 pf 6 pf 15 pf i/o timing specs: dbus[19:10] pclk_out cr0 y0 y1 6.734ns (hd 10-bit) 37.037ns (sd 10-bit) 20 % 80 % tr 20 % 80 % tf cb1 10-bit sdr mode: toh tod toh tr/tf (min) cload tod tr/tf (max) cload toh tr/tf (min) cload tod tr/tf (max) cload dbus 19.400ns 0.400ns 22.200ns 1.400ns 19.400ns 0.400ns 22.200ns 1.400ns stat 19.400ns 0.500ns 22.200ns 1.600ns 19.400ns 0.400ns 22.200ns 1.500ns 10bsd mode 3.3v 1.8v 6 pf 15 pf 6 pf 15 pf GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 35 of 104 fi g ure 4- 6 :p c lk to data an d c ontrol s i g nal output timin g - s dr mo d e 2 i/o timing specs: dbus[9:0] pclk_out cb0 cr0 cb1 6.734ns (3g 20-bit) 13.468ns (hd 20-bit) 74.074ns (sd 20-bit) 20 % 80 % tr 20 % 80 % tf cr1 20-bit sdr mode: toh tod dbus[19:10] y0 y1 y2 y3 toh tr/tf (min) cload tod tr/tf (max) cload toh tr/tf (min) cload tod tr/tf (max) cload dbus 1.000ns 0.400ns 3.700ns 1.400ns 1.000ns 0.400ns 3.700ns 1.400ns stat 1.000ns 0.500ns 4.100ns 1.600ns 1.000ns 0.400ns 4.400ns 1.500ns 20b3g and 20bhd modes 3.3v 6 pf 15 pf 1.8v 6 pf 15 pf toh tr/tf (min) cload tod tr/tf (max) cload toh tr/tf (min) cload tod tr/tf (max) cload dbus 38.000ns 0.400ns 41.000ns 1.400ns 38.000ns 0.400ns 41.000ns 1.400ns stat 38.000ns 0.500ns 41.000ns 1.600ns 38.000ns 0.400ns 41.000ns 1.500ns 20bsd mode 3.3v 1.8v 6 pf 15 pf 6 pf 15 pf GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 36 of 104 fi g ure 4-7:p c lk to data an d c ontrol s i g nal output timin g - ddr mo d e the GS2961A has a 20-bit output parallel bus, which can be configured for different output formats as shown in table 4-5 . i/o timing specs: 3.367ns dbus[19:10] pclk_out y0 y1 cr0 cb1 y2 6.734ns 20 % 80 % tr 20 % 80 % tf cr1 y3 ddr mode: toh tod toh tod toh tr/tf (min) cload tod tr/tf (max) cload toh tr/tf (min) cload tod tr/tf (max) cload dbus 0.450ns 0.400ns 1.900ns 1.500ns 0.400ns 0.300ns 1.800ns 1.100ns stat 0.450ns 0.500ns 2.200ns 1.600ns 0.450ns 0.400ns 2.500ns 1.500ns 10b3g mode 3.3v 1.8v 6 pf 15 pf 6 pf 15 pf table 4-5: GS2961A output video data format selections output data format pin/register bit settings dout[9:0] dout[19:10] 20bit /10bit rate_ sel0 rate_ sel1 smpte_ bypass dvb-asi 20- b it d emultiplexe d hd format hi g hlow low hi g hlow c hroma luma 20- b it d ata output hd format hi g h low low low low data data 20- b it d emultiplexe d s d format hi g hhi g hx hi g hlow c hroma luma 20- b it d ata output s d format hi g hhi g h x low low data data 10- b it multiplexe d 3 g ddr format low low hi g hhi g h low driven low data s tream one/ data s tream two* 10- b it multiplexe d hd format low low low hi g h low driven low luma/ c hroma 10- b it d ata output hd format low low low low low driven low data GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 37 of 104 4.9.2 parallel output in smpte mode when the device is operatin g in smpte mode (smpte_bypass = high and dvb_asi = low), data is output in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit pin. when operating in 20-b it mode (20bit/10bit = high), the output data is demultiplexed luma and chroma data for sd and hd data rates, and data stream 1 and data stream 2 for the 3g data. when operating in 10-b it mode (20bit/10bit = low), the output data is multiplexed luma and chroma data for sd and hd data rates, and multiplexed data stream 1 and data stream 2 for the 3g data. in this mode, the data is presented on the dout[19:10] pins, with dout[9:0] being forced low. 4.9.3 parallel output in dvb-asi mode in dvb-asi mode, the 20bit/10bit pin must be set low to configure the output parallel bus for 10-bit operation. dvb-asi mode is enabled when the auto/man bit is low, smpte_bypass pin is low and the dvb_asi pin is high. the extracted 8-bit data is presented on do ut[17:10] such that dout[17:10] = hout ~ aout, where aout is the least significant bit of the decoded transport stream data. in addition, the dout19 and dout18 pins ar e configured as dvb- asi status signals worderr and syncout respectively. 10- b it multiplexe d s d format low hi g hx hi g h low driven low luma/ c hroma 10- b it d ata output s d format low hi g h x low low driven low data 20- b it d emultiplexe d 3 g format hi g hlow hi g hhi g hlowdata s tream two* data s tream one* dvb-a s i format low hi g hx ? hi g h dout19 = word_err dout18 = s yn c _out dout17 = h_out dout1 6 = g _out dout15 = f_out dout14 = e_out dout13 = d_out dout12 = c _out dout11 = b_out dout10 = a_out *in 3 g mo d e, the d ata streams c an b e swappe d at the output throu g h the host interfa c e. note: when in auto mo d e, swap rate_ s el with rate_det. table 4-5: GS2961A output video data format selections (continued) output data format pin/register bit settings dout[9:0] dout[19:10] 20bit /10bit rate_ sel0 rate_ sel1 smpte_ bypass dvb-asi GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 38 of 104 syncout is high whenever a k28.5 sync character is output from the device. worderr is high whenever the device has detected a running disparity error or illegal code word. 4.9.4 parallel output in data-through mode this mode is enabled when the smpte_bypass and dvb_asi pins are low. in this mode, data is passed to the output bus without any decoding, descrambling or word-alignment. the output data width (10-bit or 20-bit) is controlled by the setting of the 20bit/10bit pin. note: in order to use data-through mode, a 3g-b input signal must be connected at the input of the device when the switch is made from auto mode to data-through mode. 4.9.5 parallel output clock (pclk) the frequency of the pclk output signal of the GS2961A is determined by the output data rate and the 20bit/10bit pin setting. table 4-6 lists the output signal formats according to the data format sele cted in manual mode (auto/man bit in the host interface is set low), or detected in auto mode (auto/man bit in the host interface is set high). table 4-6: GS2961A pclk output rates output data format pin/control bit settings pclk rate 20bit/ 10bit rate_det0 rate_det1 smpte_ bypass dvb-asi 20- b it d emultiplexe d hd format hi g hlowlowhi g h low 74.25 or 74.25/1.001mhz 20- b it d ata output hd format hi g h low low low low 74.25 or 74.25/1.001mhz 20- b it d emultiplexe d s d format hi g hhi g hxhi g hlow 13.5mhz 20- b it d ata output s d format hi g hhi g hxlowlow13.5mhz 20- b it d emultiplexe d 3 g format hi g hlowhi g hhi g h low 148.5 or 148.5/1.001mhz 10- b it multiplexe d 3 g ddr format low low hi g hhi g h low 148.5 or 148.5/1.001mhz 10- b it multiplexe d hd format low low low hi g h low 148.5 or 148.5/1.001mhz 10- b it d ata output hd format low low low low low 148.5 or 148.5/1.001mhz 10- b it multiplexe d s d format low hi g hxhi g h low 27mhz GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 39 of 104 4.9.6 ddr parallel clock timing the GS2961A has the ability to transmit 10-bit parallel video data with a ddr (dual data rate) pixel clock over a single-ended interface. ddr mode can be enabled when the sdi data bandwidth is 3gb/s. in this case, the 10-bit parallel data rate is 297mb/s, and the frequency of the ddr clock is 148.5m hz (10-bit output in 3g mode). the ddr pixel clock avoids the need to oper ate a high-drive pixel clock at 297mhz. this reduces power consumption, clock drive strength, and noise generation, and precludes from generating excess ive emi had pclk on the board have to ru n at 297mhz. it also enables easier board routing and avoids the need to use the higher-speed i/os on fpgas, which may require more expensive speed grades. figure 4-8 and figure 4-9 show how the ddr interface operates. the pixel clock is transmitted at half the data rate, and the interleaved data is sampled at the receiver on both clock edges. fi g ure 4-8:ddr vi d eo interfa c e - 3 g level a 10- b it d ata output s d format low hi g h x low low 27mhz 10- b it a s i output s d format low hi g hxlowhi g h 27mhz table 4-6: GS2961A pclk output rates (continued) output data format pin/control bit settings pclk rate 20bit/ 10bit rate_det0 rate_det1 smpte_ bypass dvb-asi y2 cb1 cr1 cb2 cr2 cb3 cr3 cb4 cr4 y3 y4 y5 y6 y7 y8 y9 20-bit bus (transition rate = 74.25mhz) y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 cb 0 cb 1 cb 2 cb 3 cb 4 cr 0 cr 1 cr 2 cr 3 cr 4 pclk (148.5mhz) y0 cb0 y1 cr0 10-bit bus (transition rate = 148.5mhz) GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 40 of 104 fi g ure 4-9:ddr vi d eo interfa c e - 3 g level b the GS2961A has the ability to shift the setup/ hold window on the receive interface, by using an on-chip delay line to shift the phase of pclk with respect to the data bus. the timing of the pclk output, relative to the data, can be adjusted through the host interface registers. address 06ch contains the delay line controls: bit[5] (del_line_clk_sel) is a coarse delay adjustment that selects between the default (nominal) pclk phase and a quad rature phase, for a 90o phase shift. bits[4:0] (del_line_offset) comprise a fine delay adjustment to shift the pclk in 40ps increments (typical conditions). the maximum fine delay adjustment is approximately 1.2ns under nominal conditions. an example delay adjustment over min/typ/max conditions is illustrated in figure 4-10 . the target delay is 0.84 ns under typical conditions (approximately 45o pclk phase shift), and requires a control word setting of 0x0014 for address 0x006c. dout0[9:0] dout1[9:0] cb[2] 0 y[2] 0 cr[2] 0 y[2] 1 y[2] 2 y[2] 3 y[2] 4 cr[2] 1 cb[2] 1 cb[2] 2 cb[3] 0 y[3] 0 cr[3] 0 y[3] 1 y[3] 2 y[3] 3 y[3] 4 cr[3] 1 cb[3] 1 cb[3] 2 cb[3] 0 y[3] 0 cr[3] 0 y[3] 1 y[3] 2 y[3] 3 y[3] 4 cr[3] 1 cb[3] 1 cb[3] 2 cb[2] 0 y[2] 0 cr[2] 0 y[2] 1 y[2] 2 y[2] 3 y[2] 4 cr[2] 1 cb[2] 1 cb[2] 2 dout1[9:0] data stream 1 data stream 2 20-bit bus (transition rate = 74.25mhz) pclk (148.5mhz) 10-bit bus (transition rate = 148.5mhz) GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 41 of 104 fi g ure 4-10:delay a d justment ran g es 4.10 timing signal generator the GS2961A has an intern al timing signal generator whic h is used to ge nerate digital fvh timing reference signals, to detect and correct certain error conditions and automatic video standard detection. the timing signal generator is only operational in smpte mode (smpte_bypass = high). the timing signal generator consists of a number of counters and comparators operating at video pixel and video line rates. these counters maintain information about the total line length, active line length, total number of lines per field/frame and total active lines per field/frame for the re ceived video standard. it takes one video frame to obtain full synchronization to the received video standard. note : both 8-bit and 10-bit trs words are identified by the device. once synchronization has been achieved, the timing signal generator continues to monitor the received trs timing information to maintain synchronization. the timing signal generator re-synchronizes all pixel and line based counters on every received trs id. note that for correct operation of the timing signal generator, the sw_en input pin must be set low, unless manual synchronous switching is enabled ( section 4.10.1 ). pclk 6.734ns 3.367ns offset [5] = 1 (90o phase shift) 1.684ns 0.842ns ranges: pclk (min) 6.734ns 3.367ns 1.684ns pclk (typ) pclk (max) 0.58ns delay 0.84ns delay 1.38ns delay 90o phase shift typical 45o phase shift GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 42 of 104 4.10.1 manual switch line lock handling the principle of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timing and alignment, whereas the vertical timing remains in synchronization - i.e. switching between video sources of the same format. to account for the horizontal disturbance caused by a synchronous switch, the word alignment block and timing signal generator automatically re-synchronizes to the new timing immediately if the synchronous switch happens during the designated switch line, as defined in smpte re commended practice rp168-2002. the device samples the sw_en pin on every pclk cycle. when a logic low to high transition on this pin is detected anywhere within the active line, the word alignment block and timing signal generator re-synchronize immediately to the next trs word. this allows the system to force immediate lock on any line, if the switch point is non-standard. to ensure proper switch line lock handling, the sw_en signal should be asserted high anywhere within the active portion of the line on which the switch has taken place, and should be held high for approximately one video line. after this time period, sw_en should be de-asserted. sw_en should be held low during normal device operation. note : it is the rising edge of the sw_en signal, which generates the switch line lock re-synchronization. this edge must be in the active portion of the line containing the video switch point. fi g ure 4-11: s wit c h line lo c kin g on a non- s tan d ar d s wit c h line eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav anc active picture eav anc sav switch point trs position eav anc active picture sav eav anc sav anc active picture data out active picture eav anc sav eav anc sav sw_en switch video source 1 to 2 eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav active picture eav anc sav switch point eav anc active picture sav eav anc sav active picture data out switch video source 2 to 1 eav anc sav active picture eav anc sav re-synchronization sw_en re-synchronization trs position GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 43 of 104 4.10.2 automatic switc h line lock handling the synchronous switch point is defined for all major video standards in smpte rp168-2002. the device automati cally re-synchronizes the word alignment block and timing signal generator at the switch point, based on the detected video standard. the device, as described in section 4.10.1 and figure 4-11 above, implements the re-synchronization process automatically, every field/frame. the switch line is defined as follows: ? for 525 line interlaced systems: resynchroniz ation takes place at then end of lines 10 & 273 ? for 525 line progressive systems: resynchronization takes place at then end of line 10 ? for 625 line interlaced systems: resynchroniz ation takes place at then end of lines 6 & 319 ? for 625 line progressive systems: resynchronization takes place at then end of line 6 ? for 750 line progressive systems: resynchronization takes place at then end of line 7 ? for 1125 line interlaced systems: resynchroniz ation takes place at then end of lines 7 & 568 ? for 1125 line progressive systems: resynchronization takes place at then end of line 7 note : unless indicated by smpt e 352m payload identifier packets, the GS2961A does not distinguish between 1125- line progressive segmente d-frame (psf) video and 1125-line interlaced video oper ating at 25 or 30fps. howeve r. psf video operating at 24fps is detected by the device. a full list of all major video standards and switching lines is shown in table 4-7 . 4.10.3 switch line lock handling during level b to level a conversion when 3g data is detected by the GS2961A, and level b to level a conver sion is enabled, the device only supports a limited phase offset between two synchronous video sources if a synchronous switch is implemented. if the synchronous switch point results in an ?extended? active video period, the GS2961A only re-synchro nizes to the following trs id if the phase di fference between the two sources is less than or equal to 10 s. if the phase difference is greater than 10 s, the GS2961A takes one additional line to re-synchronize. in this case, the user may observe a missing h pulse on the line following the switch line, on the h timing output. note that this 10 s constraint is only valid when level b to level a conversion is enabled, and only when the synchronous switch point results in an extended active video area. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 44 of 104 table 4-7: switch line position for digital systems system frame rate & structure pixel structure signal standard parallel interface serial interface line no. 1125 6 0/p 1920x1080 4:2:2 274m + rp211 292 7 50/p 274m + rp211 6 0/i 274m + rp211 7/5 6 9 50/i 274m + rp211 30/p 274m + rp211 7 25/p 274m + rp211 24/p 274m + rp211 30/psf 274m + rp211 25/psf 274m + rp211 24/psf 274m + rp211 750 6 0/p 1280x720 4:2:2 29 6 m 292 7 50/p 29 6 m 30/p 29 6 m 25/p 29 6 m 24/p 29 6 m 6 25 50/p 720x57 6 4:2:2 bt.1358 349m 292 6 bt.1358 347m 344m bt.1358 bt.1358 bt.13 6 2 4:2:0 bt.1358 349m 292 bt.1358 bt.1358 bt.13 6 2 50/i 9 6 0x57 6 4:2:2 bt. 6 01 349m 292 6 /319 bt. 6 01 bt. 6 5 6 259m 720x57 6 4:4:4:4 bt.799 349m 292 bt.799 347m 344m bt.799 bt.799 344m bt.799 bt.799 ? 4:2:2 bt. 6 01 349m 292 bt. 6 01 125m 259m GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 45 of 104 4.11 programmable multi-function outputs the GS2961A has 6 multi-function output pins , stat [5:0], which ar e programmable via the host interface to output one of the following signals: 525 59.94/p 720x483 4:2:2 293m 349m 292 10 293m 347m 344m 293m 293m 294m 4:2:0 293m 349m 292 293m 293m 294m 59.94/i 9 6 0x483 4:2:2 2 6 7m 349m 292 10/273 2 6 7m 2 6 7m 259m 720x483 4:4:4 2 6 7m 349m 292 2 6 7m 347m 344m 2 6 7m rp174 344m 2 6 7m rp175 rp175 4:2:2 125m 349m 292 125m 125m 259m hd- s dti p or psf stru c ture 1920x1080 4:2:2 274m 274m + 348m 292 7 i stru c ture 274m 7/5 6 9 p stru c ture 1280x720 29 6 m29 6 m + 348m 7 s dti 50/i 720x57 6 4:2:2 bt. 6 5 6 bt. 6 5 6 + 305m 259m 6 /319 59.94/i 720x483 125m 125m + 305m 10/273 table 4-7: switch line position for digital systems (continued) system frame rate & structure pixel structure signal standard parallel interface serial interface line no. table 4-8: output signals available on programmable multi-function pins status signal selection code default output pin h/h s yn c (a cc or d in g to tim_8 6 1 pin) s e c tion 4.12 0000 s tat 0 v/v s yn c (a cc or d in g to tim_8 6 1 pin) s e c tion 4.12 0001 s tat 1 f/de (a cc or d in g to tim_8 6 1 pin) s e c tion 4.12 0010 s tat 2 lo c ked s e c tion 4.7 0011 s tat 3 y/1an c s e c tion 4.17 0100 s tat 4 c /2an c s e c tion 4.17 0101 ? data error s e c tion 4.1 6 0110 s tat 5 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 46 of 104 4.12 h:v:f timing signal generation the GS2961A extracts critical timing parameters from the received trs words. horizontal blanking (h), vertical blanking (v ), and field odd/even (f) timing are output on the stat[2:0] pins by default. using the h_config bit in the host interface, the h signal timing can be selected as one of the following: 1. active line blanking (h_config = low) - the h output is high for the horizontal blanking period, including the eav trs words. 2. trs based blanking (h_config = high) - th e h output is set high for the entire horizontal blanking period as indicated by the h bit in the received trs signals. the timing of these signals is shown in figure 4-15 below. note : both 8-bit and 10-bit trs words are identified by the device. fi g ure 4-12:h:v:f output timin g - 3 g level a an d hdtv 20- b it mo d e video error 0111 ? edh dete c ted 1001 ? c arrier dete c t 1010 ? rate_det0 1011 ? rate_det1 1100 ? note: ea c h of the s tat[5:0] pins are c onfi g ura b le in d ivi d ually usin g the re g ister b its in the host interfa c e; s tat[5:0]_ c onfi g (008h/009h). table 4-8: output signals available on pr ogrammable multi-function pins (continued) status signal selection code default output pin pclk luma data chroma data h 000 000 3ff 000 000 3ff v f xyz (sav) 000 000 3ff 000 000 3ff xyz (sav) xyz (eav) xyz (eav) 000 000 3ff 3ff 000 000 pclk (hd) h v f multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) pclk (3g ddr) 000 000 3ff 3ff 000 000 xyz (eav) multiplexed y?cbcr data (hd) multiplexed ds1/ds2 data (3g) h v f pclk (hd) pclk (3g ddr) h signal timing: h_config = low h_config = high hvf timingat sav hvf timingat eav xyz (eav) xyz (sav) xyz (sav) GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 47 of 104 fi g ure 4-13:h:v:f output timin g - 3 g level a an d hdtv 10- b it mo d e 3 g level b 20- b it mo d e, ea c h 10- b it stream fi g ure 4-14:h:v:f output timin g - 3 g level b 10- b it mo d e fi g ure 4-15:h:v:f output timin g - hd 20- b it output mo d e fi g ure 4-1 6 :h:v:f output timin g - hd 10- b it output mo d e fi g ure 4-17:h:v:f output timin g - s d 20- b it output mo d e fi g ure 4-18:h:v:f output timin g - s d 10- b it output mo d e 3ff pclk (ddr) h v f multiplexed linka/linkb data 3ff 3ff 3ff 000 000 000 000 000 000 000 000 xyz (sav) xyz (sav ) xyz (sav) xyz (sav ) multiplexed linka/linkb data pclk (ddr) h v f 3ff 000 000 000 000 000 000 000 000 xyz (eav) xyz (eav) xyz (eav) xyz (eav) 3ff 3ff 3ff h signal timing: h_config = low h_config = high hvf timingat eav hvf timingat sav p c lk lu m a d a t a in p u t c hroma data input h x y z (eav) 000 000 3ff 000 000 3ff v f 000 000 3ff 000 000 3ff x y z (eav) x y z ( s av) x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h hvf timin g at s av 000 000 3ff 3ff 000 000 p c lk multiplexed y' cbc r d a t a in p u t h v f hvf timin g at eav p c lk 000 000 3ff 3ff x y z (eav) 000 000 multiplexed y' cbc r d a t a in p u t h v f x y z (eav) xyz ( s av) x y z ( s av) p c lk c hroma data input luma data input h 000 3ff x y z (eav) 000 v f 000 3ff 000 h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h x y z ( s av) multiplexed y' cbc r data input p c lk h v f x y z (eav) 000 000 3ff 000 000 3ff x y z ( s av) h s i g nal timin g : h_ c onfi g = low h_ c onfi g = hi g h GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 48 of 104 4.12.1 cea-861 timing generation the GS2961A is capable of generating cea 861 timing instead of smpte hvf timing for all of the supported video formats. this mode is selected when the tim_861 pin is high. horizontal sync (hsync), vertical sync (v sync), and data enab le (de) timing are output on the stat[2:0] pins by default. table 4-9 shows the cea-861 formats supported by the GS2961A: 4.12.1.1 vertical timing when cea861 timing is sele cted, the device outputs standards compliant cea861 timing signals as shown in the figures below; for example 240 active lines per field for smpte 125m. the register bit trs_861 is us ed to select dfp timing generator mode which follows the vertical blanking timing as defined by the embedded trs code words. this setting is helpful for 525i. when trs_861 is set low, de will go high for 480 lines out of 525. when trs_861 is set high, de will go high for 487 lines out of 525. the timing of the cea 861 timing refere nce signals can be found in the cea 861 specifications. for information, they are included in the following diagrams. these diagrams may not be comprehensive. table 4-9: supported cea-861 formats format cea-861 format vd_std[5:0] 720(1440) x 480i @ 59.94/ 6 0hz 6 & 7 1 6 h, 17h, 19h, 1bh 720(1440) x 57 6 i @ 50hz 21 & 22 18h, 1ah 1280 x 720p @ 59.94/ 6 0hz 4 20h, 00h 1280 x 720p @ 50hz 19 24h, 04h 1920 x 1080i @ 59.94/ 6 0hz 5 2ah, 0ah 1920 x 1080i @ 50hz 20 2 c h, 0 c h 1920 x 1080p @ 29.97/30hz 34 1 2bh, 0bh 1920 x 1080p @ 25hz 33 2 2dh, 0dh 1920 x 1080p @ 23.98/24hz 32 30h, 10h 1920 x 1080p @ 59.94/ 6 0hz 1 6 1 2bh 1920 x 1080p @ 50hz 31 2 2dh notes: 1,2: timin g is i d enti c al for the c orrespon d in g formats. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 49 of 104 fi g ure 4-19:h:v:de output timin g 1280 x 720p @ 59.94/ 6 0 (format 4) table 4-10: cea861 timing formats format parameters 4 h:v:de input timin g 1280 x 720p @ 59.94/ 6 0hz 5 h:v:de input timin g 1920 x 1080i @ 59.94/ 6 0hz 6 &7 h:v:de input timin g 720 (1440) x 480i @ 59.94/ 6 0hz 19 h:v:de input timin g 1280 x 720p @ 50hz 20 h:v:de input timin g 1920 x 1080i @ 50hz 21&22 h:v:de input timin g 720 (1440) x 57 6 @ 50hz 1 6 h:v:de input timin g 1920 x 1080p @ 59.94/ 6 0hz 31 h:v:de input timin g 1920 x 1080p @ 50hz 32 h:v:de input timin g 1920 x 1080p @ 23.94/24hz 33 h:v:de input timin g 1920 x 1080p @ 25hz 34 h:v:de input timin g 1920 x 1080p @ 29.97/30hz 1 66 0 total horizontal c lo c ks per line 1280 c lo c ks for a c tive vi d eo data ena b le 220 c lo c ks 40 370 110 h s yn c pro g ressive frame: 30 verti c al blankin g lines 720 a c tive verti c al lines 1 6 50 c lo c ks data ena b le h s yn c 110 v s yn c 2 6 0 745 74 6 747 748 749 750 1 2 3 4 5 6 7 25 2 6 745 74 6 750 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 50 of 104 fi g ure 4-20:h:v:de output timin g 1920 x 1080i @ 59.94/ 6 0 (format 5) 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c v s yn c 1123 1124 1125 1 2 3 4 5 6 7 8 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 fiel d 1: 22 verti c al blankin g lines 2200 c lo c ks 88 19 20 21 5 6 0 5 6 1 5 6 2 192 540 a c tive verti c al lines per fiel d 540 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines 192 88 2200 c lo c ks 1100 v s yn c data ena b le h s yn c 5 6 0 5 6 1 5 6 2 5 6 3 5 6 4 5 6 5 5 66 5 6 7 5 6 8 5 6 9 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 51 of 104 fi g ure 4-21:h:v:de output timin g 720 (1440) x 480i @ 59.94/ 6 0 (format 6 &7) fi g ure 4-22:h:v:de output timin g 1280 x 720p @ 50 (format 19) 1440 c lo c ks for a c tive vi d eo 27 6 data ena b le 171 6 total horizontal c lo c ks per line h s yn c data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c 114 c lo c ks 124 38 fiel d 1: 22 verti c al blankin g lines 171 6 c lo c ks 238 240 a c tive verti c al lines per fiel d ~ ~ ~ ~ 38 240 a c tive verti c al lines per fiel d fiel d 2: 23 verti c al blankin g lines ~ ~ 524 525 1 2 3 4 5 6 7 8 9 21 22 ~ ~ ~ ~ 238 38 171 6 c lo c ks 858 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 66 2 6 7 2 6 8 2 6 9 270 271 524 525 1 284 285 2 6 1 2 6 2 2 6 3 220 c lo c ks 1280 c lo c ks for a c tive vi d eo 700 data ena b le h s yn c v s yn c 745 74 6 747 748 749 750 1 2 3 4 5 6 7 data ena b le h s yn c 1980 total horizontal c lo c ks per line 40 440 pro g ressive frame: 30 verti c al blankin g lines 1980 c lo c ks 440 745 74 6 2 6 0 720 a c tive verti c al lines ~ ~ ~ ~ ~ ~ ~ 25 2 6 ~ ~ ~ ~ 750 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 52 of 104 fi g ure 4-23:h:v:de output timin g 1920 x 1080i @ 50 (format 20) 148 clocks 1920 clocks for active video 720 data enable hsync 2640 total horizontal clocks per line 44 528 vsync 1123 1124 1125 1 2 3 4 5 6 7 8 data enable hsync field 1: 22 vertical blanking lines 2640 clocks 528 19 20 21 560 561 562 192 540 active vertical lines per field 540 active vertical lines per field field 2: 23 vertical blanking lines 192 528 2640 clocks 1320 vsync data enable hsync 560 561 562 563 564 565 566 567 568 569 570 582 583 584 1123 1124 1125 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 53 of 104 fi g ure 4-24:h:v:de output timin g 720 (1440) x 57 6 @ 50 (format 21 & 22) fi g ure 4-25:h:v:de output timin g 1920 x 1080p @ 59.94/ 6 0 (format 1 6 ) 1440 c lo c ks for a c tive vi d eo 288 data ena b le 1728 total horizontal c lo c ks per line h s yn c 138 c lo c ks 12 6 24 data ena b le h s yn c v s yn c data ena b le h s yn c v s yn c fiel d 1: 24 verti c al blankin g lines 1728 c lo c ks 2 6 4 288 a c tive verti c al lines per fiel d ~ ~ ~ ~ 24 288 a c tive verti c al lines per fiel d fiel d 2: 25 verti c al blankin g lines ~ ~ 6 23 6 24 6 25 1 2 3 4 5 6 7 22 23 ~ ~ ~ ~ 2 6 4 24 1728 c lo c ks 8 6 4 310 311 312 313 314 315 31 6 317 318 319 320 6 23 6 24 6 25 335 33 6 310 311 312 ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2200 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 54 of 104 fi g ure 4-2 6 :h:v:de output timin g 1920 x 1080p @ 50 (format 31) fi g ure 4-27:h:v:de output timin g 1920 x 1080p @ 23.94/24 (format 32) 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 830 data ena b le h s yn c 2750 total horizontal c lo c ks per line 44 6 38 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2750 c lo c ks 6 38 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 55 of 104 fi g ure 4-28:h:v:de output timin g 1920 x 1080p @ 25 (format 33) fi g ure 4-29:h:v:de output timin g 1920 x 1080p @ 29.97/30 (format 34) 4.13 automatic video standards detection using the timing extracted from the received trs signals, th e GS2961A is able to identify the received video standard. in 3g input mode, the GS2961A measures the timing parameters of one of the two identical data streams. the rate selection/indication bits and the vd_std code may be used in combination to determine the video standard. the total samples per line, acti ve samples per line, total lines per field/frame and active lines per field/frame are all measured. four registers are provided to allow the system to read the video standard information from the device. these raster structure registers are provided in addition to the 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 720 data ena b le h s yn c 2 6 40 total horizontal c lo c ks per line 44 528 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2 6 40 c lo c ks 528 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ 148 c lo c ks 1920 c lo c ks for a c tive vi d eo 280 data ena b le h s yn c 2200 total horizontal c lo c ks per line 44 88 v s yn c 1121 1122 1123 1124 1125 1 2 3 4 5 6 7 data ena b le h s yn c pro g ressive frame: 45 verti c al blankin g lines 2220 c lo c ks 88 1121 1122 1123 1124 1125 192 1080 a c tive verti c al lines ~ ~ ~ ~ ~ ~ 41 42 ~ ~ ~ GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 56 of 104 video_format_352_a_x and video_format _352_b_x registers, and are updated once per frame at the end of line 12. the raster structure registers also cont ain three status bits: std_lock, int/prog and m. the std_lock bit is set high whenever the timing signal generator is fully synchronized to the incoming standard, and detects it as one of the supported formats. the int/prog bit is set high if the detected video standard is interlaced and low if the detected video standard is progressive. m is set high if the clock frequency includes the ?1000/1001? factor denoting a 23.98, 29.97 or 59.94hz frame rate. the video standard code is reported in the vd_std bits of the host interface register. table 4-11 describes the 5-bit codes for the recognized video standards. table 4-11: supported video standard codes smpte standard active video area rate_ det[1] hd /3g rate_ det[0] sd/hd lines per frame active lines per frame words per active line words per line vd_std [5:0] 425m (3 g level a) 4:2:2 1920x1080/ 6 0 (1:1) 1 0 1125 1080 1920 2200 2bh 1920x1080/50 (1:1) 1 0 1125 1080 1920 2 6 40 2dh 425m (3 g level b d s 1 an d d s 2) 4:2:2 1920x1080/ 6 0 (2:1) 1 0 1125 540 1920 2200 0ah 1920x1080/50 (2:1) 1 0 1125 540 1920 2 6 40 0 c h 425m (3 g ) 4:4:4 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 1 0 1125 1080 3840 4400 2ah 1920x1080/50 (2:1) or 1920x1080/25 (psf) 1 0 1125 1080 3840 5280 2 c h 1280x720/ 6 0 (1:1) 1 0 750 720 25 6 0 3300 20h 1280x720/50 (1:1) 1 0 750 720 25 6 039 6 0 24h 1920x1080/30 (1:1) 1 0 1125 1080 3840 4400 2bh 1920x1080/25 (1:1) 1 0 1125 1080 3840 5280 2dh 1280x720/25 (1:1) 1 0 750 720 25 6 0 7920 2 6 h 1920x1080/24 (1:1) 1 0 1125 1080 3840 5500 30h 1280x720/24 (1:1) 1 0 750 720 25 6 0 8250 28h 2 6 0m (hd) 1920x1035/ 6 0 (2:1) 0 0 1125 1035 1920 2200 15h 295m (hd) 1920x1080/50 (2:1) 0 0 1250 1080 1920 237 6 14h GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 57 of 104 274m (hd) 1920x1080/ 6 0 (2:1) or 1920x1080/30 (psf) 0 0 1125 1080 1920 2200 0ah 1920x1080/50 (2:1) or 1920x1080/25 (psf) 0 0 1125 1080 1920 2 6 40 0 c h 1920x1080/30 (1:1) 0 0 1125 1080 1920 2200 0bh 1920x1080/25 (1:1) 0 0 1125 1080 1920 2 6 40 0dh 1920x1080/24 (1:1) 0 0 1125 1080 1920 2750 10h 1920x1080/24 (psf) 0 0 1125 1080 1920 2750 11h 1920x1080/25 (1:1) ? 0 0 1125 1080 2304 2 6 40 0eh 1920x1080/25 (psf) ? em 0 0 1125 1080 2304 2 6 40 0fh 1920x1080/24 (1:1) ? 0 0 1125 1080 2400 2750 12h 1920x1080/24 (psf) ? em 0 0 1125 1080 2400 2750 13h 29 6 m (hd) 1280x720/30 (1:1) 0 0 750 720 1280 3300 02h 1280x720/30 (1:1) ? em 0 0 750 720 2880 3300 03h 1280x720/50 (1:1) 0 0 750 720 1280 1980 04h 29 6 m (hd) 1280x720/50 (1:1) ? em 0 0 750 720 1728 1980 05h 1280x720/25 (1:1) 0 0 750 720 1280 39 6 00 6 h 1280x720/25 (1:1) ? em 0 0 750 720 345 6 39 6 0 07h 1280x720/24 (1:1) 0 0 750 720 1280 4125 08h 1280x720/24 (1:1) ? em 0 0 750 720 3 6 00 4125 09h 1280x720/ 6 0 (1:1) 0 0 750 720 1280 1 6 50 00h 1280x720/ 6 0 (1:1) ? em 0 0 750 720 1440 1 6 50 01h 125m ( s d) 1440x487/ 6 0 (2:1) x 1 525 244 or 243 1440 171 6 1 6 h 1440x507/ 6 0 x 1 525 254 or 253 1440 171 6 17h 525-line 487 g eneri c x 1 525 ?? 171 6 19h 525-line 507 g eneri c x 1 525 ?? 171 6 1bh itu-r bt. 6 5 6 ( s d) 1440x57 6 /50 (2:1) or d ual link pro g ressive) x1 6 25 ? 1440 1728 18h 6 25-line g eneri c x1 6 25 ?? 1728 1ah table 4-11: supported video standard codes (continued) smpte standard active video area rate_ det[1] hd /3g rate_ det[0] sd/hd lines per frame active lines per frame words per active line words per line vd_std [5:0] GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 58 of 104 note : in certain systems, due to greater ppm offsets in the crystal, the ?m? bit may not assert properly. in such cases, bits 3:0 in register 06fh can be increased to a maximum value of 4. by default (after power up or after sy stems reset), the four raster_structure, vd_std, std_lock and int/prog fields are set to zero. these fields are also cleared when the smpte_bypass pin is low. unknown hd s d/hd = 0 0 0 ???? 1dh unknown s d s d/hd = 1 x 1 ???? 1eh unknown 3 g s d/hd = 0 1 0 ???? 3 c h 2k standards (see 4.13.1 2k support ) 2048-2- 200xx (4:2:2) 2048x1080/30 (1:1) 0 0 1125 1080 2048 2200 31h 2048x1080/25 (1:1) 0 0 1125 1080 2048 2 6 40 32h 2048x1080/24 (1:1) 0 0 1125 1080 2048 2750 33h 2048x1080/ 6 0 (1:1) 1 0 1125 1080 2048 2200 37h 2048x1080/50 (1:1) 1 0 1125 1080 2048 2 6 40 38h 2048x1080/48 (1:1) 1 0 1125 1080 2048 2750 39h 2048-2- 200x (4:4:4) 2048x1080/30 (1:1) 1 0 1125 1080 2048 2200 34h 2048x1080/25 (1:1) 1 0 1125 1080 2048 2 6 40 35h 2048x1080/24 (1:1) 1 0 1125 1080 2048 2750 3 6 h non s mpte or 2048-2- 200xx (4:2:2) level b d s 1 an d d s 2 2048x1080/ 6 0 (2:1) 0 (1) 0 1125 540 2048 2200 3dh 2048x1080/50 (2:1) 0 (1) 0 1125 540 2048 2 6 40 3eh 2048x1080/48 (2:1) 0 (1) 0 1125 540 2048 2750 3fh non s mpte unknown 2k x 0 ?? 2048 ? 3ah notes: 1. the line num b ers in b ra c kets refer to version zero s mpte 352m pa c ket lo c ations, if they are d ifferent from version 1 . 2. the part may provi d e full or limite d fun c tionality with stan d ar d s that are not in c lu d e d in this ta b le. please c onsult a s emte c h te c hni c al representative. 3. for s d- s di streams, the d evi c e c an report an in c orre c t m value when s mpte-352m pa c kets are present. table 4-11: supported video standard codes (continued) smpte standard active video area rate_ det[1] hd /3g rate_ det[0] sd/hd lines per frame active lines per frame words per active line words per line vd_std [5:0] GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 59 of 104 4.13.1 2k support in order to fully support 2k standards with out customer intervention, semtech provides fpga code for enhancing th e GS2961A's 2k capability. the features of the 2k fpga enhancement are: ? automatic video standard detection for 2k standards ? 1/1.001 rate detection for 2k standards ? cea-861 timing generation for 2k standards ? automatic enabling of audio extraction this enhancement is an in terface between the GS2961A and the customer system. the behaviour of the GS2961A with or without th e additional 2k enha ncement fpga code is identical from a user-perspective. fi g ure 4-30:2k feature enhan c ement GS2961A host interface control pll 2 1 gib_mux 0 1 gib_buf level_b fpga level_b vid_out[19:0] hvf[2:0] wo_2k stat3 stat4 stat5 GS2961A_gspi_sdi GS2961A_gspi_cs GS2961A_gspi_sclk GS2961A_gspi_sdout reset host_gspi_cs host_gspi_sclk host_gspi_sdi host_gspi_sdout pclk pclk_div2 smpte_bypass_i tim_861 clk_27m_ref dy_in_i[9:0] dc_in_i[9:0] fvh_o[2:0] host_gspi_busy level_b rate_m_o std_2k_det_o dy_out_o[9:0] dc_out_o[9:0] fvh_i[2:0] GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 60 of 104 4.14 data format de tection & indication in addition to detecting the video standard, the GS2961A detects the data format, i.e. sdti, sdi, tdm data (smpte 346m), etc. this information is represented by bits in the data_format_dsx register accessible through the host interface. data format detection is only carried out when the locked signal is high. by default (at power up or after system reset), the data_format_dsx register is set to fh (undefined). this register is also set as undefined when the locked signal is low and/or the smpte_bypass pin is low. the data format is determined using the following criteria: ? if trs id words are detected but no sdti header or tdm header is detected, then the data format is sdi ? if trs id words are detected and the sdti header is available then the format is sdti ? if trs id words are detected and the tdm data header is detected then the format is tdm video ? no trs words are detected, but the pll is locked, then the data format is unknown note : two data format sets are provided for hd video rates. this is because the y and cr/cb channels can be used separately to carry sdti data streams of different data formats. in sd video mode, only the y data format register contains the data, and the c register is set to fh (undefined format). table 4-12: data format register codes ydata_format[3:0] or cdata_format[3:0] data format remarks 0h ~ 05h s dti s mpte 321m, s mpte 322m, s mpte 32 6 m 6 h s di ? 7h reserve d ? 8h tdm s mpte 34 6 m 9h hd- s dti ? ah ~ eh reserve d ? fh non- s mpte d ata format dete c te d d ata format is not s mpte. lo c ked = low. note: this data format re g ister is invali d in s mpte_bypa ss mo d e. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 61 of 104 4.15 edh detection 4.15.1 edh packet detection the GS2961A determines if ed h packets are present in th e incoming video data and asserts the edh_detect status according to the smpte standard. edh_detect is set high when edh packets have been detected and remains high until edh packets are no longer present. it is set low at the end of the vertical blanking (falling edge of v) if an edh packet has not been detected during vertical blanking. edh_detect can be programmed to be output on the multi-function output port pins. the edh_detect bit is also available in the host interface. 4.15.2 edh flag detection the edh flags for ancillary data, active pictur e, and full field regions are extracted from the detected edh packets and placed in the edh_flag_in register. when the edh_flag_update_mask bit in the host interface is set high, the GS2961A updates the anci llary data, full field, and acti ve picture edh flags according to smpte rp165. the updated edh flags are available in the edh_ flag_out register. the edh packet output from the device contains these updated flags. one set of flags is provided for both fields 1 an d 2. the field 1 flag da ta is overwritten by the field 2 flag data. when edh packets are not detected, the ues flags in the edh_flag_out register are set high to signify that the received signal does not support error detection and handling. in addition, the edh_detect bit is set low. these flags are set regardless of the setting of the edh_flag_update_mask bit. edh_flag_out and edh_flag_in may be read via the host interface at any time during the received frame except on the li nes defined in smpte rp165, when these flags are updated. the GS2961A indicates the crc va lidity for both active pict ure and full field crcs. the ap_crc_v bit in the host interface indicates the active picture crc validity, and the ff_crc_v bit indicates the full field crc validity. when edh_detect = low, these bits are cleared. the edh_flag_out and edh_flag_in register values remain set until overwritten by the decoded flags in the next received edh packet. when an edh packet is not detected during vertical blanking, the flag registers ar e cleared at the end of the vertical blanking period. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 62 of 104 4.16 video signal erro r detection & indication the GS2961A includes a number of video sign al error detection fu nctions. these are provided to enhance operation of the device when operating in smpte mode (smpte_bypass = high). these features are not available in the other operating modes of the device (i.e. when smpte_bypass = low). signal errors that can be detected include: 1. trs errors. 2. hd line based crc errors. 3. edh errors. 4. hd line number errors. 5. video standard errors. the device maintains an erro r_stat_x register. each error condition has a specific flag in the error_stat_x register, which is set high whenever an error condition is detected. an error_mask register is also provided, allowing the user to select which error conditions are reported. each bit of the error_mask register corresponds to a unique error type. each bit of each error_mask register corresponds to a unique error type. by default (at power up or after system reset), all bits of the error_mask registers are zero, enabling all errors to be reported. in dividual error detection may be disabled by setting the corresponding bit high in the mask registers. error conditions are indicated by a data _error signal, which are available for output on the multifunction i/o output pins. this signal is normally high, but is set low by the device when an error condition has been detected. this signal is a logical 'nor' of the appropriate error status flags stored in the error_stat_x register, which are gated by the bit settings in the error_mask registers. when an error status bit is high and the corresponding error mask bit is low, the corresponding data_error signal is set low by the device. the error_stat_x registers, and correspondingly the data_error signal, are cleared at the start of the next video field or when read via the host interface, which ever condition occurs first. all bits of the error_stat_x registers are also cleared under any of the following conditions: 1. locked signal = low. 2. smpte_bypass = low. 3. when a change in video standard has been detected. 4. reset_trst = low table 4-13 shows the error_stat_x regist er and error_mask_x register. note : since the error indication registers are cleared once per field, if an external host micro is polling the error registers periodica lly, an error flag may be missed if it is intermittent, and the polling frequency is less than the field rate. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 63 of 104 note : in 3g level b mode, separate video error mask registers exist for link a and link b. the GS2961A distinguishes between level a and level b mappings at 3gb/s. when level b data is detected, error detection is enabled separately for data stream 1 and data stream 2 (link a and link b, respectively). therefore, a second set of error status and mask registers is available for data stream 2, and is only valid when 3gb/s level b data is detected by the device. 4.16.1 trs error detection trs error flags are generated by the gs2 961a under the followi ng two conditions: 1. a phase shift in received trs timing is observed on a non-switching line. 2. the received trs hammi ng codes are incorrect. both sav and eav trs words are checked for timing and data integrity errors. for hd mode, only the y channel trs codes are checked for errors. for 3g mode level a signals, only data stream one trs codes are checked for errors. for 3g level b signals, the y channel trs codes of both link a and link b are checked for errors. both 8-bit and 10-bit trs code words are checked for errors. the sav_err bit of the error_stat_x register is set high when an sav trs error is detected. the eav_err bit of the error_stat_x register is set high when an eav trs error is detected. 4.16.2 line based crc error detection the GS2961A calculates line ba sed crcs for hd and 3g vide o signals. crc calculations are done for each 10-bit channel (y and c for hd video, ds1 an d ds2 for 3g video). table 4-13: error status register and error mask register video error status register video error mask register s av_err (02h, 03h) s av_err_ma s k (037h, 038h) eav_err (02h, 03h) eav_err_ma s k (037h, 038h) y c r c _err (02h, 03h) y c r c _err_ma s k (037h, 038h) cc r c _err (02h, 03h) cc r c _err_ma s k (037h, 038h) lnum_err (02h, 03h) lnum_err_ma s k (037h, 038h) y cs _err (02h, 03h) y cs _err_ma s k (037h, 038h) ccs _err (02h, 03h) ccs _err_ma s k (037h, 038h) ap_ c r c _err (02h) ap_ c r c _err_ma s k (037h) ff_ c r c _err (02h) ff_ c r c _err_ma s k (037h) vd_ s td_err (02h, 03h) vd_ s td_err_ma s k (037h) GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 64 of 104 these calculated crc values are compared with the received crc values. if a mismatch in the calculated and received crc values is detected for y channel data (data stream 1 for 3g video), the ycrc_err bit in the error_stat_x register is set high. if a mismatch in the calculated and received crc values is detected for c channel data (data stream 2 for 3g video), the ccrc_err bit in the error_stat_ x register is set high. y or c crc errors are also generated if crc values are not embedded. line based crc errors are only generated wh en the device is operating in hd and 3g modes. note : by default, 8-bit to 10-bit trs remapping is enabled. if an 8-bit input is used, the hd crc check is based on the 10-bit remapped value, not the 8-bit value, so the crc error flag is incorrectly assert ed and should be ignored. if 8-bit to 10-bit remapping is enabled, then crc correction and insertion should be enabled by setting the crc_ins_mask bit in the iopr oc_disable register low. this ensures that the crc values are updated. 4.16.3 edh crc error detection the GS2961A also calculates full field (ff) an d active picture (ap) crc's according to smpte rp165 in support of er ror detection and handling packets in sd signals. these calculated crc values are compared with the received crc values. error flags for ap and ff crc errors are provid ed and each error flag is a logical or of field 1 and field 2 error conditions. the ap_crc_err bit in the video_error_stat_x register is set high when an active picture crc mismatch has been detected in field 1 or 2. the ff_crc_err bit in the video_error_sta t_x register is set high when a full field crc mismatch has been detected in field 1 or 2. edh crc errors are only indicated when the device is operating in sd mode and when the device has correctly received edh packets. 4.16.4 hd & 3g line number error detection if a mismatch in the calculated and received line numbers is detected, the lnum_err bit in the video_error_stat_x register is set high. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 65 of 104 4.17 ancillary data detection & indication the GS2961A detects ancillary data in both the vertical and hori zontal ancillary data spaces. status signal outputs y/1anc and c/2anc are provided to indicate the position of ancillary data in the output data streams. these signals may be selected for output on the multi-function i/o port pins (stat[5:0]). the GS2961A indicates the presen ce of all types of ancillary data by detecting the 000h, 3ffh, 3ffh (00h, ffh, ffh for 8-bit video) ancillary data preamble. note: both 8 and 10-bit ancillary data preambles are detected by the device. by default (at power up or after system reset) the GS2961A indi cates all types of ancillary data. up to 5 types of ancillary data can be specifically programmed for recognition. for hd video signals, ancillary data may be placed in both the y and cb/cr video data streams separately. for sd video signals, the ancillary data is mult iplexed and combined into the ycbcr data space. for 3g signals, ancillary data may be placed in either or both of the virtual interface data streams. both data streams are examined for ancillary data. for a 3g data stream formatted as per level a mapping: ? the ancillary data is placed in data stream 1 first, with overflow into data stream 2 ? smpte 352m packets are duplic ated in both data streams for a 3g data stream formatted as per level b mapping: ? each multiplexed data stream forming the 3g signal contains ancillary data embedded according to smpte 291m ? each multiplexed data stre am forming the 3g signal contains smpte 352m packets embedded according to smpte 425m when operating in hd mode, the y/1anc signal is high whenever ancillary data is detected in the luma data stream, and c/2anc is high whenever ancillary data is detected in the chroma data stream. the signals are asserted high at the start of the ancillary data preamble, and remain high until after th e ancillary data checksum. when detecting ancillary data in 3g level a data, the y/1anc status output is high whenever data stream 1 ancillary data is detected and the c/2anc status output is high whenever data stream 2 ancillary data is detected. when detecting ancillary data in 3g level b data, the y/1anc status output is high whenever data stream 1 ancillary data is detected on either y or c channels and the c/2anc status output is high whenever data stream 2 ancillary da ta is detected on either y or c channels. when operating in sd mode, the y/1anc an d c/2anc signals depend on the output data format. for 20-bit demu ltiplexed data, the y/1anc and c/2anc signals operate independently to indicate the first and last ancillary data word position in the luma and/or chroma data streams. for 10-bit mult iplexed data, the y/1anc signal is high whenever ancillary data is detected, and the c/2anc signal is always low. when operating in 3g modes, the y/1anc an d c/2anc flags are both zero if the 10-bit multiplexed output fo rmat is selected. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 66 of 104 these status signal outputs are synchronous with pclk and may be used as clock-enables for external logic, or as wr ite-enables for an external fifo or other memory devices. the operation of the y/1anc and c/2anc signals is shown below in figure 4-31 . note 1: when i/o processing is disabled, th e y/1anc and c/2anc flags may toggle, but they are invalid and should be ignored. note 2: in 3g level b mode, if the anc_ext_sel_ds2_ds1 bit is high and the anc_data_delete bit is high, the y/1a nc and c/2anc flags are not valid. note 3: for 3g level b data, the y/1anc flag identifies all anc data on data stream 1 (link a), whether it is embedded in the y or c component ? anc data is not identified separately for each component. similarly, the c/2anc flag identifies all anc data on data stream 2 (link b), whether it is embedded in the y or c component. fi g ure 4-31:y/1an c an d c /2an c s i g nal timin g 4.17.1 programmable ancillary data detection as described above in section 4.17 , the GS2961A detects and in dicates all ancillary data types by default. it is possible to program which ancillary data types are to be detected and indicated. up to 5 different ancillary data types may be programmed fo r detection by the GS2961A in the anc_type_ds1 registers for sd, hd and 3g level a data. pclk luma data out chroma data out y/1anc c/2anc pclk luma data out y/1anc pclk chroma data out anc data detection - hdtv 10 bit output mode pclk multiplexed y'cbcr ycsum ccsum y did canc 3ff 000 000 f f 3 f f 3 f f 3 anc data detection - hdtv 20 bit output mode blank blank anc data dc dbn did csum anc data csum anc data dc dbn did anc data 3ff 3ff 3ff 3ff 000 000 anc data detection - sdtv 20 bit output mode csum blank anc data anc data dc did anc data blank blank anc data anc data anc data dbn anc data 3ff blank 000 3ff anc data detection - sdtv 10 bit output mode csum blank anc data dc dbn did anc data 3ff 3ff 000 multiplexed y'cbcr y/1anc y/1anc c/2anc c/2anc GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 67 of 104 when so programmed, the GS2961A only in dicates the presence of the specified ancillary data types, ignoring all other ancillary data. for each data type to be detected, the user must program the did and/or sdid of that ancillary data type. in the case where no did or sdid values are programmed, the GS2961A indicates the presence of all ancillary data. in the case where one or more, did and/or sdid values have been programmed, then only those matching data types are detected and indicated. the timing of the y/1anc and c/2anc signals in this case is as shown in figure 4-31 . the GS2961A compares th e received did and/or sdid wi th the programmed values. if a match is found, ancillary data is indicated. for any did or sdid value set to zero, no comparison or match is made. for example, if the did is programmed and the sdid is not programmed, the GS2961A only detects a match to the did value. if both did and sdid values are non-zero, th en the received ancilla ry data type must match both the did and sdid before y/1anc and/or c/2anc is set high. note 1: for 3g level b data, the anc_type_ds1 registers are valid for data stream 1, and a second set of five anc_type register s (anc_type_ds2) is provided for detection of specific ancillary data in data stream 2. note 2: smpte 352m payload ident ifier packets and error detection and handling (edh) packets are always detect ed by the GS2961A, irrespecti ve of the settings of the anc_type registers. 4.17.2 smpte 352m payload identifier the GS2961A automatically extrac ts the smpte 352m payload identifier pr esent in the input data stream for sd, hd, and 3g level a signals. the four word payload identifier packets are written to video_format_x_ds1 and video_format_x_ds2 bits accessible through the host interface. the device also in dicates the versio n of the payload packet in the version_352m bit of the data_format_dsx register. when the smpte 352m packet is formatted as a ?version 1? packet, the versio n_352m bit is set high, when the packet is formatted as a ?version 2? packet, this bit is set low. the video_format_352_a_x and video_format_352_b_x registers are only updated if there are no checksum errors in the received smpte 352m packets. by default (at power up or after system reset), the video_format_x_ds1 and video_format_x_ds2 bits are set to 0, indicating an undefined format. note 1: when 3g level b data is detected by the device, the user needs to extract the smpte 352m payload identifier packets by using the anc packet extraction block - they are not detected and extracted automatically. in this case: ? the vd_std_err bit is not valid ? 352m extraction is only done on one data stream or the other, not both simultaneously (link a or link b selected via the host interface) ? previously embedded 352m packets can be deleted on one data stream only (using the anc_data_delete bit, see section 4.18.8 ), but these packets are replaced with 10-bit y/c blanking values only GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 68 of 104 ? it is necessary to manually extract the smpte 352m data by programming the did, sdid and line number information into the anc data extraction block note 2: smpte 352m packet regenera tion is enabled by default for 3g level b inputs, and should be disabled through the host interface if level b to level a conversion is not enabled. 4.17.2.1 smpte 352m payload identifier usage the smpte 352m payload identifier is used to confirm the vide o format identi fied by the automatic video standards detection block (see section 4.17.4 ) 4.17.2.2 3g smpte 352m packets following level b to level a conversion after level b to level a conversion, modified payload data must be programmed via the host interface into the video_format_352_x_x registers and automatically inserted by the GS2961A on the correct smpte 352m line number. smpte 352m packets are embedd ed in both data streams. previously embedded 352m packets may be deleted from one data stream only (using the anc_data_delete bit, see section 4.18.8 ), but these packets are replaced with 10-bit y/c blanking values. note: pre-existing smpt e 352m packets that are not deleted are re-mapped to different line numbers during conversion to level a formatting. these packets should be ignored by the system, since they ar e on non-standard smpte 352m lines. 4.17.3 ancillary data checksum error the GS2961A calculates checksums fo r all received ancillary data. these calculated checksums are compared with the received ancillary data checksum words. if a mismatch in the calculated and received checksums is detected, then a checksum error is indicated. when operating in hd mode, the device makes comparis ons on both the y and c channels separately. if an error condition in the y channel is detected, the ycs_err bit table 4-14: smpte 352m packet data bit name bit name description r/w default video_format_4_d s 1 a dd ress: 01ah 15-8 s mpte 352m byte 4 data is availa b le in this re g ister when vi d eo payloa d i d entifi c ation pa c kets are d ete c te d in the d ata stream. r0 video_format_3_d s 1 a dd ress: 01ah 7-0 s mpte 352m byte 3 r0 video_format_2_d s 1 a dd ress: 019h 15-8 s mpte 352m byte 2 r0 video_format_2_d s 1 a dd ress: 019h 7-0 s mpte 352m byte 1 r0 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 69 of 104 in the video_error_stat_x register is set high. if an error condition in the c channel is detected, the ccs_err bit in the vide o_error_stat_x register is set high. when operating in 3g level a mode, the device makes comparisons on both the y (data stream 1) and c (data stream 2) channels separately. if an error condition in the y channel is detected, the ycs_err bit in the video_error_stat_x register is set high. if an error condition in the c channel is detected, the ccs_err bit in the video_error_stat_x regi ster is set high. when operating in 3g level b mode, the device makes comparisons on both the y channel and the c channel of both link a and link b. when operating in sd mode, only the ycs_err bit is set high when checksum errors are detected. 4.17.3.1 programmable ancillary data checksum calculation as described above, the GS2961A calculates and compares checks um values for all ancillary data types by default. it is possible to program which ancillary data types are checked as described in section 4.17.1 . when so programmed, the GS2961A only ch ecks ancillary data checksums for the specified data types, ignoring all other ancillary data. the ycs_err and/or ccs_err bits in the vi deo_error_stat_x register are only set high if an error condition is detected for the programmed ancillary data types. 4.17.4 video standard error if a mismatch between the received smpte 352m packets and the calculated video standard occurs, the GS2961A indicates a video standa rd error by setting the vd_std_err bit of the video_error_stat_x register high. the device detects the smpt e 352m packet version as defined in the smpte 352m standard. if the incoming packet is version zero, then no comparison is made with the internally generated payload information and the vd_std_err bit is not set high. note 1: if the received smpte 352m packet in dicates 25, 30 or 29.97psf formats, the device only indicates an error when the video format is actually progressive. the device detects 24 and 23.98psf vide o standards and perform erro r checking at these rates. note 2: the vd_std_err bit should be ignored in all 3g modes. note 3: vd_std_err_ds1 is set incorrectl y for a 1920x1080/psf/24 payload id. to resolve this issue, choose one of the two methods. ? set the vd_std_err_ds1 mask bit high in the error_mask_1 register to avoid having incorrect assertion of the data_error pin. ? monitor the received smpte st0352 pa cket in the video_format_352_a_1 and video_format_352_b_1 regi sters and compare that to the video format identified in the vd_std_ds1 bits in the data_format_ds1 register. then, make the determination of whether or not there is a mismatch on their own. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 70 of 104 4.18 signal processing in addition to error detectio n and indication, the GS2961A can also correct errors, inserting corrected code words, checksums and crc values into the data stream. the following processing can be performed by the GS2961A: 1. trs error correcti on and insertion. 2. hd line based crc co rrection and insertion. 3. edh crc error correc tion and insertion. 4. hd line number error correction and insertion. 5. illegal code re-mapping. 6. ancillary data checksum er ror correction and insertion. 7. smpte 372m (level b to level a) conversion. all of the above features are only available in smpte mode (smpte_bypass = high). to enable these features, the ioproc_en/dis pin must be set high, and the individual feature must be enabled via bits in the ioproc_disable register. the ioproc_disable register contains one bit for each processing feature allowing each one to be enabled/disabled individually. by default (at power up or after system reset), all of the ioproc_disable register bits are low, enabling all of the processing features. to disable an individual proc essing feature, set the corresponding ioproc_disable bit high in the ioproc_disable register. table 4-15: ioproc_disable register bits processing feature ioproc_disable register bit tr s error c orre c tion an d insertion tr s _in s y an d c line b ase d c r c error c orre c tion c r c _in s y an d c line num b er error c orre c tion lnum_in s an c illary d ata c he c k sum c orre c tion an c _ c he c k s um_in s ertion edh c r c error c orre c tion edh_ c r c _in s ille g al c o d e re-mappin g ille g al_word_remap h timin g si g nal c onfi g uration h_ c onfi g up d ate edh fla g s edh_fla g _update_ma s k an c illary data extra c tion an c _data_ext re g eneration of 352m pa c kets re g en_352m GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 71 of 104 4.18.1 trs correc tion & insertion when trs error correction and insertio n is enabled, the GS2961A generates and overwrites trs code words as required. trs word generation and insertion is performed using the timing generated by the timing signal generator, providing an elem ent of noise immunity over using just the received trs information. this feature is enabled when the ioproc_en/dis pin is high and the trs_ins_disable bit in the ioproc _disable register is set low. note: inserted trs code words are always 10- bit compliant, irrespective of the bit depth of the incoming video stream. 4.18.2 line based crc correction & insertion when crc error correction and insertio n is enabled, the GS2961A generates and inserts line based crc words into both the y and c channels of the data stream. line based crc word generation and insertion only occurs in hd and 3g modes, and is enabled in when the ioproc_en/dis pin is high and the crc_ins_dsx_mask bit in the ioproc_x register is set low. 4.18.3 line number erro r correction & insertion when line number error corr ection and insertio n is enabled, the GS2961A calculates and inserts line numbers into the output data stream. re-calculated line numbers are inserted into both the y and c channels. line number generation is in accordance with the relevant hd or 3g video standard as determined by the automatic standards detection block. this feature is enabled when the device is operating in hd or 3g modes, the ioproc_en/dis pin is high and the lnum_ins_dsx_mask bit in the ioproc_x register is set low. 4.18.4 anc data checksum er ror correction & insertion when anc data checksum error correction and insertion is enabled, the GS2961A generates and inserts ancillary data checksums for all ancillary data words by default. where user specified ancillary data has been programmed (see section 4.17.1 ), only the checksums for the programmed ancillary data are corrected. this feature is enabled when the ioproc_en/dis pin is high and the anc_checksum_insertion_dsx_mask bit in the ioproc_x register is set low. 4.18.5 edh crc corr ection & insertion when edh crc error co rrection and insertion is enab led, the GS2961A generates and overwrites full field and active picture crc check-words. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 72 of 104 additionally, the device sets the active picture and full field crc 'v' bits high in the edh packet. the ap_crc_v and ff_crc_v register bits only report the received edh validity flags. edh ff and ap crc's are only inserted when the device is operating in sd mode, and if the edh data packet is detected in the received video data. although the GS2961A modifies and insert s edh crc's and edh packet checksums, edh error flags are only updated when the edh_flag_update_mask bit is low. this feature is enabled in sd mode, when the ioproc_en/dis pin is high and the edh_crc_ins_mask bit in the ioproc_1 register is set low. 4.18.6 illegal word re-mapping all words within the active picture (outside the horizontal and vertical blanking periods), between the values of 3fch and 3ffh are re-mapped to 3fbh. all words within the active picture area betw een the values of 000h and 003h are remapped to 004h. this feature is enabled when the ioproc_en/dis pin is high and the illegal_word_remap_dsx_mask bit in the ioproc_x register is set low. 4.18.7 trs and ancillary data preamble remapping 8-bit trs and ancillary data preambles are re-mapped to 10-bit values. 8-bit to 10-bit mapping of trs headers is only supporte d if the trs values are 3fc 000 000. other values such as 3fd, 3fe, 3ff, 001, 002 and 003 are not supported. this feature is enabled by default, and cannot be disabl ed via the ioproc_x register. 4.18.8 ancillary data extraction ancillary data may be extrac ted externally from the gs 2961a output stream using the y/1anc and c/2anc signal s, and external logic. as an alternative, th e GS2961A includes a fifo, which extr acts ancillary data using read access via the host in terface to ease system implementa tion. the fifo stores up to 2048 x 16 bit words of ancillary data in two separate 1024 wo rd memory banks. the device writes the contents of anc packets into the fifo, starting with the first ancillary data flag (adf), followed by up to 1024 words. all data identification (did), secondary data identification (sdid), data count (dc), user data, and checksum words are written into the device memory. the device detects ancillary data packet did's placed anywhere in the video data stream, including the active picture area. ancillary data from the y channel or data stream one is placed in the least significant word (lsw) of the fifo, allocated to th e lower 8 bits of each fifo address. ancillary data from the c channel or data st ream two is placed in the most significant word (msw) (upper 8 bits) of each fifo address. note: please refer to the anc insertion and extraction application note (doc id: 53410), for discrete steps and example of ancillary data extraction. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 73 of 104 in sd mode, ancillary data is placed in th e lsw of the fifo. the msw is set to zero. if the anc_type registers are all set to zero, the device extracts all types of ancillary data. if programmable ancillary data extraction is required, then up to five types of ancillary data to be extracted can be programmed in the anc_type registers (see section 4.17.1 ). additionally, the lines from which the packets are to be extracted can be programmed into the anc_linea[10:0] and anc_lineb[10:0] regi sters, allowing an cillary data from a maximum of two lines per frame to be extracted. if only one line number register is programmed (with the other set to zero), ancillary data packets are extracted from one line per frame only. when both registers are se t to zero, the device extracts packets from all lines. to start ancillary data extraction, the anc_data_ext_mask bit of the host interface must be set low. ancillary data packet extr action begins in the following frame (see figure 4-32: ancillary da ta extraction - step a ). fi g ure 4-32:an c illary data extra c tion - s tep a ancillary data is written into bank a until full. the y/1anc and c/2anc output flags can be used to determine the length of the ancillary data extracted and when to begin reading the extracted data from memory. while the anc_data_ext_mask bit is set low, the anc_data_switch bit can be set high during or after reading the extracted data. new data is then written into bank b (up to 1024 x 16-bit words), at the corre sponding host interf ace addresses (see figure 4-33: ancillary data extraction - step b ). anc data anc data anc data anc data anc data anc data anc data 0 1023 application layer read pointer internal write pointer bank a anc_data_switch = low 0 1023 bank b 800h 800h bffh bffh GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 74 of 104 fi g ure 4-33:an c illary data extra c tion - s tep b to read the new data, toggle the anc_data _switch bit low. the old data in bank a is cleared to zero and extraction continues in bank b (see figure 4-34: ancillary data extraction - step c ). fi g ure 4-34:an c illary data extra c tion - s tep c anc data anc data anc data anc data anc data anc data anc data anc data anc data 0 1023 application layer read pointer internal write pointer bank a anc_data_switch = high 0 1023 bank b 800h 800h bffh bffh anc data anc data anc data anc data anc data anc data anc data 0 1023 application layer read pointer internal write pointer bank a anc_data_switch = low 0 1023 bank b 800h 800h bffh bffh GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 75 of 104 if the anc_data_switch bit is not toggled, extracted data is written into bank b until full. to continue extraction in bank a, the anc_data_switch bit must be toggled high (see figure 4-35: ancillary da ta extraction - step d ). fi g ure 4-35:an c illary data extra c tion - s tep d toggling the anc_data_switch bit low returns the process to step a ( figure 4-32 ). note: toggling the anc_data_switch must occur at a time when no extraction is taking place, i.e. when the both the y/1anc and c/2anc signals are low. to turn extraction off, the anc_data_ext_mask bit must be set high. in hd mode, the device can de tect ancillary data packets in the luma video data only, chroma video data only, or both. by default (at power-up or after a system reset), the device extracts ancillary data pa ckets from the luma channel only. in 3g mode level a, the device can detect ancillary data packets in luma video (data stream one) only, chroma vi deo (data stream two) only, or both. by default (at power-up or after a system reset), the device extracts ancillary data packets from data stream one only. in 3g mode level b mode, the device can detect ancillary data packets in luma video only, chroma video only, or both from either link a or link b. selection of link a or link b for anc data extraction is done via the host interface. by default (at power-up or after a system reset), the device extracts ancillary data packets from link a luma only. to extract packets from the chroma/data stream two channel only, the hd_anc_c2 bit of the host interface must be set high. to extract packets from both luma/data stream one and chroma/data stream two video data, the hd_anc_y1_c2 bit must be set high (the setting of the hd_anc_c2 bit is ignored). 0 1023 application layer read poi nter internal write pointer bank a anc_data_switch = high 0 1023 bank b anc data anc data anc data anc data anc data anc data anc data anc data anc data 800h 800h bffh bffh GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 76 of 104 the default setting of both the hd_anc_c2 and hd_anc_y1_c2 is low. the setting of these bits is ignored when the device is configured for sd video standards. ancillary data packet extraction and deletion is disabled when the ioproc_en/dis pin is set low. after extraction, the ancillary data may be deleted from the video stream by setting the anc_data_del bit of the host interface high. when set high, all existing ancillary data is removed and replaced with blanking values. if any of the anc_type registers are programmed with a did and/or did and sdid, only the ancillary data packets with the matching ids are deleted from the video stream. note 1: after the ancillary data determined by the anc_type_x_apx registers has been deleted, other existing ancillary data may not be contiguous. the device does not concatenate the remaining ancillary data. note 2: reading extracted ancillary data from the host interface must be performed while there is a valid video signal present at the serial input and the device is locked (locked signal is high). 4.18.9 level b to level a conversion when ioproc_2 register bit level_b2a_ conv_disable_mask is high (default), the GS2961A does not conver t 3g level b streams betw een level a and level b mapping formats. when level_b2a_conv_disable_mask is low, the GS2961A co nverts a 3g 1080p level b stream to the level a mapping format, as per smpte 425m. the device assumes that link a and link b are phase-aligned at the transmitter. the output data are line multiplexed such that the data content from link a and link b are assembled in a continuous fashion, at twice the input data rate. extracted timing reference information is used to trigger a line counter which embeds the correct line number according to smpte 425m. the level b/a conversion acts only on the active picture, anc data can become corrupt outside of this region. in order to ensure that the embedded anc data remains valid, we recommend extracting the anc data with the receiver prior to the level b/a conversion taking place. note 1: if level b/a conversion is enabled, previous 352m payload id packets are not deleted from the data stream. note 2: when level b/a conversion is enabled, timing reference information (fvh as well as cea861 timing) present on the stat outputs is not phase-aligned with the output video data, and should not be used for line or frame synchronization activities. being that cea 861 timing is derived from (fvh) timing reference information, it too should not be used. during level b to level a conversion, it is advised that the user generates the h and v timing sign als from the embedded trs words. note 3: if the GS2961A sees a synchronous sw itch where the difference in phases between two level b inputs is greater than ~10.7 s, the user may observe a missing h pulse on the line following the switch li ne, when level b/a conversion is enabled. note 4: discontinuities in the line of video at the input of the level b to a converter can cause erroneous mapping to the level a format. therefore, when enabling b to a GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 77 of 104 conversion, it is recommended to reset the level b to a converter with the following sequence: 1. assert the b to a converter reset by writing '1' to bit 3 of register 05eh. 2. monitor h-pulse for a high-to-low transition. 3. de-assert the b to a converter reset by writin g '0' to bit 3 of register 05eh. this must be completed at the beginning of sav and should be completed in 1920 pclk periods. 4.19 gspi - ho st interface the gspi, or gennum serial peripheral interfac e, is a 4-wire interface provided to allow the system to access additional status an d control information through configuration registers in the GS2961A. the gspi is comprised of a serial data inpu t signal (sdin), serial data output signal (sdout), an active low chip select (cs ), and a burst clock (sclk). because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when jtag/host is high, the jtag interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals must be provided by the system. the sdout pin is a non-clocked loop-through of sdin and may be connected to the sdin of another device, allowing multiple devices to be connected to the gspi chain. see section 4.19.2 for details. the interface is illustrated in the figure 4-36 below. fi g ure 4-3 6 : gs pi appli c ation interfa c e c onne c tion all read or write access to the GS2961A is initiated and te rminated by the system host processor. each access always begins wi th a command/address word, followed by a data write to, or data read from, the GS2961A. application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 GS2961A GS2961A cs GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 78 of 104 4.19.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. fi g ure 4-37: c omman d wor d format command words are clocked into the GS2961A on the rising edge of the serial clock sclk, which operates in a burst fashion. the chip select (cs ) signal must be set low a minimum of 1.5ns (t0 in figure 4-39 ) before the first clock edge to ensure proper operation. when the auto-increment bit is set low, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word is written into the address specified in the command word, and subsequent data words are written into incremental addresses from the first data word. this facilitates multiple address writes without sending a command word for each data word. note : the rsv bits in the gspi command word can be set to zero as placeholder, though these bits are not used. 4.19.2 data read or write access during a read sequence (command word r/w bi t set high) serial data is transmitted or received msb first, synchronous with the rising edge of the serial clock sclk. the chip select (cs ) signal must be set low a minimum of 1.5ns (t0 in figure 4-39 ) before the first clock edge to ensure proper operation. the first bit (msb) of the serial output (sdout) is available (t5 in figure 4-40 ) following the last falling sclk edge of the read command word, the remaining bits are clocked out on the negative edges of sclk. note: when several devices are connected to the gspi chain, only one cs may be asserted during a read sequence. during a write sequence (command word r/w bi t set low), a wait state of 37.1ns (t4 in figure 4-39 ) is required between the command word and the following data word. this wait state must also be maintained be tween successive command word/data word write sequences. when auto increment mode is selected (autoinc = 1), the wait state must be maintained between successive data words after the initial command word/data word sequence. during the write sequence, all command and following data words input at the sdin pin are output at the sdout pin unchanged. when several devices are connected to the gspi chain, data can be written simultaneously to all the devices which have cs set low. fi g ure 4-38:data wor d format r/w rsv rsv autoinc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 msb lsb d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 msb lsb GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 79 of 104 4.19.3 gspi timing write and read mode timing for the gspi interface; fi g ure 4-39:write mo d e fi g ure 4-40:rea d mo d e fi g ure 4-41: gs pi time delay r/w rsv rsv au to _in c a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d1 1 d1 0 sclk _tclk cs _tms sdin _tdi sdout _tdo t 0 t 3 t 1 t 2 r/w rsv rsv au to _inc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a1 1 a1 0 d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d1 1 d1 0 t 8 t 4 t 7 r/w rsv rsv au t o _inc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a11 a10 d15d14d13d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d1 1 d 1 0 sclk _tclk cs _ t ms sdin _tdi sdout _tdo t 5 r/w r sv r sv au t o _inc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a1 1 a 1 0 t 6 sdin_tdi data_0 sdin_tdi to sdout_tdo combinational path for daisy chain connection of multiple GS2961A devices. sdout_tdo data_0 t delay table 4-16: gspi time delay parameter symbol conditions min ty p max units delay time t delay 50% levels; 1.8v operation ?? 13.1 ns delay time t delay 50% levels; 3.3v operation ?? 9.7 ns GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 80 of 104 this timing must be satisfied across all ambient temperature and power supply operating conditions, as described in the electrical characteristics on page 14 . table 4-17: gspi timing parameters ( 50% levels; 3.3v or 1.8v operation) parameter symbol min ty p max units cs low b efore sc lk risin g e dg et 0 1.5 ?? ns sc lk perio d t 1 1 6 . 6 7 ?? ns sc lk d uty c y c le t 2 40 50 6 0% input d ata setup time t 3 1.5 ?? ns time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? write c y c le t 4 p c lk (mhz) ns ?? ns unlo c ke d 100 27.0 37.1 74.25 13.5 148.5 6 .7 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? rea d c y c le. t 5 p c lk (mhz) ns ?? ns unlo c ke d ? 27.0 148.4 74.25 53.9 148.5 27 time b etween en d of c omman d wor d (or d ata in auto-in c rement mo d e) an d the first sc lk of the followin g data wor d ? rea d c y c le - an c fifo rea d t 5 222. 6 ?? ns output hol d time (15pf loa d )t 6 1.5 ?? ns cs hi g h after last sc lk risin g e dg et 7 p c lk (mhz) ns ?? ns unlo c ke d 445 27.0 37.1 74.25 13.5 148.5 6 .7 input d ata hol d time t 8 1.5 ?? ns GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 81 of 104 4.20 host interf ace register maps table 4-18: configuration and status registers address register name bit name bit description r/w default 000h iopro c _1 r s vd 15 reserve d . r 0 tr s _word_remap_d s 1 _di s able 14 disa b les 8- b it tr s wor d remappin g for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. r/w 0 r s vd 13 reserve d . r/w 0 edh_fla g _update _ma s k 12 disa b les up d atin g of edh error fla g s. r/w 0 edh_ c r c _in s _ma s k11disa b les edh_ c r c error c orre c tion an d insertion. r/w 0 h_ c onfi g 10 s ele c ts the h b lankin g in d i c ation: 0: a c tive line b lankin g - the h output is hi g h for all the horizontal b lankin g perio d , in c lu d in g the eav an d s av tr s wor d s. 1: tr s b ase d b lankin g - the h output is set hi g h for the entire horizontal b lankin g perio d as in d i c ate d b y the h b it in the re c eive d tr s si g nals. this si g nal is only vali d when tim_8 6 1 is set to '0' (via pin or host interfa c e). r/w 0 an c _data_ext_ma s k9disa b les an c illary d ata extra c tion fifo. r/w 0 r s vd 8 reserve d . r/w 0 tim_8 6 1_pin_di s able 7 disa b le tim_8 6 1 pin c ontrol when set to '1', an d use timin g _8 6 1 b it instea d . r/w 0 timin g _8 6 1 6s ele c ts the output timin g referen c e format: 0 = di g ital fvh timin g output; 1 = c ea-8 6 1 timin g output. r/w 0 r s vd 5 reserve d . r/w 0 ille g al_word_remap _d s 1_ma s k 4disa b les ille g al wor d remappin g for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. r/w 0 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 82 of 104 000h iopro c _1 an c _ c he c k s um _in s ertion_d s 1_ma s k 3disa b les insertion of an c illary d ata c he c ksums for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. r/w 0 c r c _in s _d s 1_ma s k2disa b les insertion of hd/3 g c r c wor d s for 3 g level b data s tream 1, 3 g level a, an d hd inputs. r/w 0 lnum_in s _d s 1_ma s k1disa b les insertion of line num b ers for 3 g level b data s tream 1, 3 g level a, an d hd inputs. r/w 0 tr s _in s _d s 1_ma s k0disa b les insertion of tr s wor d s for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. r/w 0 001h iopro c _2 r s vd 15 reserve d . r/w n/a noninv 14 with di s b_autdet set hi g h, if this b it is asserte d (hi g h), for c es non-inverte d mpe g -2 d e c o d in g . if d easserte d (low), for c es inverte d mpe g -2 d e c o d in g . appli c a b le in dvb-a s i mo d e only. r/w 0 di s b_autdet 13 disa b les auto d ete c tion of inverte d dvb a s i mpe g -2 d ata when hi g h. when low, noninv is i g nore d an d the dvb d e c o d er auto d ete c ts for inverte d mpe g -2 d ata. appli c a b le in dvb-a s i mo d e only. r/w 0 tr s _word_remap_d s 2 _di s able 12 disa b les 8- b it tr s wor d remappin g in data s tream 2 (3 g level b only). r/w 0 r s vd 11 reserve d . r/w 0 re g en_352m_ma s k10disa b les re g eneration of the s mpte 352m pa c ket for 3 g level b d ata. note: this b it nee d s to b e ena b le d via the host interfa c e to d isa b le s mpte 352m pa c ket g eneration. it is stron g ly re c ommen d e d to set this b it low only when level b to level a c onversion is ena b le d . r/w 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 83 of 104 001h iopro c _2 d s _ s wap_3 g 9 s waps data s tream 1 (d s 1) an d data s tream 2 (d s 2) at the output in 3 g mo d e. in 20- b it output mo d e, d s 1 shall b e present on dout pins [19:10] an d d s 2 shall b e present on dout pins [9:0] b y d efault. when d s _ s wap_3 g is set to '1', d s 2 shall b e present on dout pins [19:10] an d d s 1 shall b e present on dout pins [9:0] in 10- b it (ddr) output mo d e, d s 2 shall pre c e d e d s 1 b y d efault. when d s _ s wap_3 g is set to '1', d s 1 shall pre c e d e d s 2. r/w 0 level_b2a_ c onv _di s able_ma s k 8disa b le c onversion of a 3 g level b input to a 3 g level a format. only effe c tive if in 3 g level b mo d e. default is a c tive hi g h ( d isa b le d ), so level b inputs are formatte d as level b outputs. r/w 1 an c _ext_ s el_d s 2_d s 1 7 s ele c ts d ata stream to extra c t an c d ata from (vali d for 3 g level b d ata). r/w 0 r s vd 6 -5 reserve d . r/w 0 ille g al_word_remap _d s 2_ma s k 4disa b les ille g al wor d remappin g in data s tream 2 (3 g level b only). r/w 0 an c _ c he c k s um _in s ertion_d s 2_ma s k 3disa b les insertion of an c illary d ata c he c ksums in data s tream 2 (3 g level b only). r/w 0 c r c _in s _d s 2_ma s k2disa b les insertion of c r c wor d s in data s tream 2 (3 g level b only). r/w 0 lnum_in s _d s 2_ma s k1disa b les insertion of line num b ers in data s tream 2 (3 g level b only). r/w 0 tr s _in s _d s 2_ma s k0disa b le insertion of tr s wor d s in data s tream 2 (3 g level b only). r/w 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 84 of 104 002h error_ s tat_1 r s vd 15-11 reserve d . ro c w 0 vd_ s td_err_d s 110vi d eo s tan d ar d error in d i c ation for hd an d s d inputs. ro c w0 ff_ c r c _err 9 edh full frame c r c error in d i c ation. ro c w0 ap_ c r c _err 8 edh a c tive pi c ture c r c error in d i c ation. ro c w0 r s vd 7 reserve d . ro c w 0 ccs _err_d s 1 6c hroma an c illary d ata c he c ksum error in d i c ation for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. ro c w0 y cs _err_d s 15luma an c illary d ata c he c ksum error in d i c ation for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. ro c w0 cc r c _err_d s 14 c hroma c r c error in d i c ation for 3 g level b data s tream 1, 3 g level a, an d hd inputs. ro c w0 y c r c _err_d s 13luma c r c error in d i c ation for 3 g level b data s tream 1, 3 g level a, an d hd inputs. ro c w0 lnum_err_d s 12line num b er error in d i c ation for 3 g level b data s tream 1, 3 g level a, an d hd inputs. ro c w0 s av_err_d s 11 s av error in d i c ation for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. ro c w0 eav_err_d s 1 0 eav error in d i c ation for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. ro c w0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 85 of 104 003h error_ s tat_2 r s vd 15-7 reserve d . ro c w 0 ccs _err_d s 2 6c hroma an c illary d ata c he c ksum error in d i c ation for data s tream 2 (3 g level b only). ro c w0 y cs _err_d s 25luma an c illary d ata c he c ksum error in d i c ation for data s tream 2 (3 g level b only). ro c w0 cc r c _err_d s 24 c hroma c r c error in d i c ation for data s tream 2 (3 g level b only). ro c w0 y c r c _err_d s 23luma c r c error in d i c ation for data s tream 2 (3 g level b only). ro c w0 lnum_err_d s 22line num b er error in d i c ation for data s tream 2 (3 g level b only). ro c w0 s av_err_d s 21 s av error in d i c ation for data s tream 2 (3 g level b only). ro c w0 eav_err_d s 20eav error in d i c ation for data s tream 2 (3 g level b only). ro c w0 004h edh_fla g _in edh_dete c t15em b e dd e d edh pa c ket d ete c te d .r 0 an c _ue s _in 14 an c illary d ata ? unknown error status fla g . r0 an c _ida_in 13 an c illary d ata ? internal error d ete c te d alrea d y fla g . r0 an c _idh_in 12 an c illary d ata ? internal error d ete c te d here fla g r0 an c _eda_in 11 an c illary d ata ? error d ete c te d alrea d y fla g . r0 an c _edh_in 10 an c illary d ata ? error d ete c te d here fla g . r0 ff_ue s _in 9 edh full fiel d ? unknown error status fla g . r0 ff_ida_in 8 edh full fiel d ? internal error d ete c te d alrea d y fla g . r0 ff_idh_in 7 edh full fiel d ? internal error d ete c te d here fla g . r0 ff_eda_in 6 edh full fiel d ? error d ete c te d alrea d y fla g . r0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 86 of 104 004h edh_fla g _in ff_edh_in 5 edh full fiel d ? error d ete c te d here fla g . r0 ap_ue s _in 4 edh a c tive pi c ture ? unknown error status fla g . r0 ap_ida_in 3 edh a c tive pi c ture ? internal error d ete c te d alrea d y fla g . r0 ap_idh_in 2 edh a c tive pi c ture ? internal error d ete c te d here fla g . r0 ap_eda_in 1 edh a c tive pi c ture ? error d ete c te d alrea d y fla g . r0 ap_edh_in 0 edh a c tive pi c ture ? error d ete c te d here fla g . r0 005h edh_fla g _out r s vd 15 reserve d . r 0 an c _ue s 14 an c illary d ata ? unknown error s tatus fla g . r1 an c _ida 13 an c illary d ata ? internal error dete c te d alrea d y fla g . r0 an c _idh 12 an c illary d ata ? internal error dete c te d here fla g . r0 an c _eda 11 an c illary d ata ? error dete c te d alrea d y fla g . r0 an c _edh 10 an c illary d ata ? error dete c te d here fla g . r0 ff_ue s 9 edh full fiel d ? unknown error s tatus fla g . r1 ff_ida 8 edh full fiel d ? internal error dete c te d alrea d y fla g . r0 ff_idh 7 edh full fiel d ? internal error dete c te d here fla g . r0 ff_eda 6 edh full fiel d ? error dete c te d alrea d y fla g . r0 ff_edh 5 edh full fiel d ? error dete c te d here fla g . r0 ap_ue s 4edh a c tive pi c ture ? unknown error s tatus fla g . r1 ap_ida 3 edh a c tive pi c ture ? internal error dete c te d alrea d y fla g . r0 ap_idh 2 edh a c tive pi c ture ? internal error dete c te d here fla g . r0 ap_eda 1 edh a c tive pi c ture ? error dete c te d alrea d y fla g . r0 005h edh_fla g _out ap_edh 0 edh a c tive pi c ture ? error dete c te d here fla g . r0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 87 of 104 00 6 hdata_format_ d s 1 ff_ c r c _v 15 edh full fiel d c r c vali d ity b it. r 0 ap_ c r c _v 14 edh a c tive pi c ture c r c vali d ity b it. r 0 vd_ s td_d s 1 13-8 dete c te d vi d eo s tan d ar d for 3 g level b data s tream 1, 3 g level a, hd an d s d inputs. r29 c data_format_d s 1 7-4 data format as in d i c ate d in c hroma c hannel for 3 g level b data s tream 1, hd an d s d inputs; data format as in d i c ate d in data s tream 2 for 3 g level a inputs. r15 ydata_format_d s 1 3-0 data format as in d i c ate d in luma c hannel for 3 g level b data s tream 1, hd an d s d inputs; data format as in d i c ate d in data s tream 1 for 3 g level a inputs. r15 007h data_format_ d s 2 r s vd 15-14 reserve d . r 0 vd_ s td_d s 2 13-8 dete c te d vi d eo s tan d ar d for data s tream 2 (3 g level b only). r29 c data_format_d s 2 7-4 data format as in d i c ate d in c hroma c hannel for data s tream 2 (3 g level b only). r15 ydata_format_d s 2 3-0 data format as in d i c ate d in luma c hannel for data s tream 2 (3 g level b only). r15 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 88 of 104 008h io_ c onfi g r s vd 15 reserve d .rw0 s tat2_ c onfi g 14-10 c onfi g ure s tat2 output pin: 00000: h blankin g when tim_8 6 1 = 0; h s yn c when tim_8 6 1 = 1 00001: v blankin g when tim_8 6 1 = 0; v s yn c when tim_8 6 1 = 1 00010: f b it when tim_8 6 1 = 0; data ena b le (de) when tim_8 6 1 = 1 00011: lo c ked 00100: y/1an c : an c in d i c ation ( s d), luma an c in d i c ation (hd), data s tream 1 an c d ata in d i c ation (3 g ) 00101: c /2an c : c hroma an c in d i c ation (hd) or data s tream 2 an c d ata in d i c ation (3 g ) 00110: data error 00111: vi d eo error 01000: reserve d 01001: edh dete c te d 01010: c arrier dete c t 01011: rate_det0 01100: rate_det1 01101 - 11111: reserve d rw 2 s tat1_ c onfi g 9-5 c onfi g ure s tat1 output pin. (refer to a b ove for d e c o d in g ) rw 1 s tat0_ c onfi g 4-0 c onfi g ure s tat0 output pin. (refer to a b ove for d e c o d in g ) rw 0 009h io_ c onfi g 2 r s vd 15 reserve d . rw 0 s tat5_ c onfi g 14-10 c onfi g ure s tat5 output pin. (refer to a b ove for d e c o d in g ) rw 6 s tat4_ c onfi g 9-5 c onfi g ure s tat4 output pin. (refer to a b ove for d e c o d in g ) rw 4 s tat3_ c onfi g 4-0 c onfi g ure s tat3 output pin. (refer to a b ove for d e c o d in g ) rw 3 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 89 of 104 00ah an c _ c ontrol r s vd 15-4 reserve d . rw 0 an c _data_ s wit c h3 s wit c hes b etween fifo memories. rw 0 an c _data_del 2 remove an c illary data from output vi d eo stream, set to luma an d c hroma b lankin g values. rw 0 hd_an c _y1_ c 2 1 extra c t an c illary d ata from luma an d c hroma c hannels (hd inputs) extra c t an c illary d ata from data s tream 1 an d data s tream 2 (3 g level a inputs) extra c t an c illary d ata from luma an d c hroma c hannels of data s tream 1 (3 g level b inputs, when an c _ext_ s el_d s 2_d s 1 = 0) extra c t an c illary d ata from luma an d c hroma c hannels of data s tream 2 (3 g level b inputs, when an c _ext_ s el_d s 2_d s 1 = 1) rw 0 hd_an c _ c 2 0 extra c t an c illary d ata only from c hroma c hannel (hd inputs) extra c t an c illary d ata only from data s tream 2 (3 g level a inputs) extra c t an c illary d ata only from c hroma c hannel of data s tream 1 (3 g level b inputs, when an c _ext_ s el_d s 2_d s 1 = 0) extra c t an c illary d ata only from c hroma c hannel of data s tream 2 (3 g level b inputs, when an c _ext_ s el_d s 2_d s 1 = 1) rw 0 00bh an c _line_a r s vd 15-11 reserve d . r/w 0 an c _line_a 10-0 vi d eo line to extra c t an c illary d ata from. r/w 0 00 c han c _line_b r s vd 15-11 reserve d . r/w 0 an c _line_b 10-0 s e c on d vi d eo line to extra c t an c illary d ata from. r/w 0 00dh - 00eh r s vd r s vd 15-0 reserve d . r 0 00fh an c _type_1_ap 1 an c _type1_d s 1 15-0 pro g ramma b le did/ s did pair #1 to extra c t from 3 g level b data s tream 1, 3 g level a, hd an d s d input formats ([15:8] = did, [7:0] = s did). r/w 0 010h an c _type_2_ap 1 an c _type2_d s 1 15-0 pro g ramma b le did/ s did pair #2 to extra c t from 3 g level b data s tream 1, 3 g level a, hd an d s d input formats ([15:8] = did, [7:0] = s did). r/w 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 90 of 104 011h an c _type_3 _ap1 an c _type3_d s 1 15-0 pro g ramma b le did/ s did pair #3 to extra c t from 3 g level b data s tream 1, 3 g level a, hd an d s d input formats ([15:8] = did, [7:0] = s did). r/w 0 012h an c _type_4 _ap1 an c _type4_d s 1 15-0 pro g ramma b le did/ s did pair #4 to extra c t from 3 g level b data s tream 1, 3 g level a, hd an d s d input formats ([15:8] = did, [7:0] = s did). r/w 0 013h an c _type_5 _ap1 an c _type5_d s 1 15-0 pro g ramma b le did/ s did pair #5 to extra c t from 3 g level b data s tream 1, 3 g level a, hd an d s d input formats ([15:8] = did, [7:0] = s did). r/w 0 014h an c _type_1 _ap2 an c _type1_d s 2 15-0 pro g ramma b le did/ s did pair #1 to extra c t from 3 g level b data s tream 2 ([15:8] = did, [7:0] = s did). r/w 0 015h an c _type_2 _ap2 an c _type2_d s 2 15-0 pro g ramma b le did/ s did pair #2 to extra c t from 3 g level b data s tream 2 ([15:8] = did, [7:0] = s did). r/w 0 01 6 han c _type_3 _ap2 an c _type3_d s 2 15-0 pro g ramma b le did/ s did pair #3 to extra c t from 3 g level b data s tream 2 ([15:8] = did, [7:0] = s did). r/w 0 017h an c _type_4 _ap2 an c _type4_d s 2 15-0 pro g ramma b le did/ s did pair #4 to extra c t from 3 g level b data s tream 2 ([15:8] = did, [7:0] = s did). r/w 0 018h an c _type_5 _ap2 an c _type5_d s 2 15-0 pro g ramma b le did/ s did pair #5 to extra c t from 3 g level b data s tream 2 ([15:8] = did, [7:0] = s did). r/w 0 019h video_format _352_a_1 video_format_2_d s 1 15-8 s mpte 352m em b e dd e d pa c ket ? b yte 2. r0 video_format_1_d s 17-0 s mpte 352m em b e dd e d pa c ket ? b yte 1: [7]: version i d entifier [ 6 :0]: vi d eo payloa d i d entifier. r0 01ah video_format _352_b_1 video_format_4_d s 1 15-8 s mpte 352m em b e dd e d pa c ket ? b yte 4. r0 video_format_3_d s 17-0 s mpte 352m em b e dd e d pa c ket ? b yte 3. r0 01bh video_format _352_a_2 video_format_2_d s 2 15-8 s mpte 352m em b e dd e d pa c ket ? b yte 2 (3 g data s tream 2 only). r0 video_format_1_d s 27-0 s mpte 352m em b e dd e d pa c ket ? b yte 1 (3 g data s tream 2 only): [7]: version i d entifier [ 6 :0]: vi d eo payloa d i d entifier. r0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 91 of 104 01 c hvideo_format _352_b_2 video_format_4_d s 2 15-8 s mpte 352m em b e dd e d pa c ket ? b yte 4 (3 g data s tream 2 only). r0 video_format_3_d s 27-0 s mpte 352m em b e dd e d pa c ket ? b yte 3 (3 g data s tream 2 only). r0 01dh video_format _352_in s _a video_format_2_in s 15-8 s mpte 352m pa c ket - b yte 2 to b e em b e dd e d after level b to level a c onversion. r/w 0 video_format_1_in s 7-0 s mpte 352m pa c ket - b yte 1 to b e em b e dd e d after level b to level a c onversion. r/w 0 01eh video_format _352_in s _b video_format_4_in s 15-8 s mpte 352m pa c ket - b yte 4 to b e em b e dd e d after level b to level a c onversion. r/w 0 video_format_3_in s 7-0 s mpte 352m pa c ket - b yte 3 to b e em b e dd e d after level b to level a c onversion. r/w 0 01fh ra s ter_ s tru c _ 1 r s vd 15-14 reserve d . r 0 word s _per_a c tline 13-0 wor d s per a c tive line. r 0 020h ra s ter_ s tru c _ 2 r s vd 15-14 reserve d . r 0 word s _per_line 13-0 total wor d s per line. r 0 021h ra s ter_ s tru c _ 3 r s vd 15-11 reserve d . r 0 line s _per_frame 10-0 total lines per frame. r 0 022h ra s ter_ s tru c _ 4 rate_ s el_readba c k 15-14 rea d b a c k d ete c te d d ata rate: 0 = hd, 1,3= s d, 2=3 g r0 m13 s pe c ifies d ete c te d m value 0: 1.000 1: 1.001 r0 note: in c ertain systems, d ue to g reater ppm offsets in the c rystal, the ?m ? b it may not assert properly. in su c h c ases, b its 3:0 in re g ister 0 6 fh c an b e in c rease d to a maximum value of 4. s td_lo c k12vi d eo stan d ar d lo c k. r 0 int_pro g 11 interla c e d or pro g ressive. r 0 a c tline_per_field 10-0 a c tive lines per frame. r 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 92 of 104 023h flywheel _ s tatu s r s vd 15-5 reserve d . r 0 v_lo c k_d s 24in d i c ates that the timin g si g nal g enerator is lo c ke d to verti c al timin g (3 g level b data s tream 2 only). r0 h_lo c k_d s 23in d i c ates that the timin g si g nal g enerator is lo c ke d to horizontal timin g (3 g level b data s tream 2 only). r0 r s vd 2 reserve d . r 0 v_lo c k_d s 11in d i c ates that the timin g si g nal g enerator is lo c ke d to verti c al timin g (3 g level b data s tream 1, 3 g level a, hd an d s d inputs). r0 h_lo c k_d s 10in d i c ates that the timin g si g nal g enerator is lo c ke d to horizontal timin g (3 g level b data s tream 1, 3 g level a, hd an d s d inputs). r0 024h rate_ s el r s vd 15-3 reserve d . r 0 auto/man 2dete c t d ata rate automati c ally (1) or pro g ram manually (0). r/w 1 rate_ s el_top 1-0 pro g ramma b le rate sele c t in manual mo d e: 0 = hd, 1,3= s d, 2=3 g r/w 0 025h tim_8 6 1_ format r s vd 15-7 reserve d . r 0 format_err 6 in d i c ates stan d ar d is not re c o g nize d for c ea 8 6 1 c onversion. r1 format_id_8 6 15-0 c ea-8 6 1 format id of input vi d eo stream. refer to ta b le 4-9 . r0 02 6 htim_8 6 1_ c f g r s vd 15-3 reserve d . r 0 v s yn c _invert 2 invert output v s yn c pulse. r/w 0 h s yn c _invert 1 invert output h s yn c pulse. r/w 0 tr s _8 6 10 s ets the timin g referen c e outputs to dfp timin g mo d e when set to '1'. by d efault, the timin g referen c e outputs follow c ea-8 6 1 timin g mo d e. only vali d when tim_8 6 1 is set to '1'. r/w 0 027h - 03 6 h r s vd r s vd ? reserve d . r 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 93 of 104 037h error_ma s k_1 r s vd 15-11 reserve d . r 0 error_ma s k_1 10-0 error mask for g lo b al error ve c tor (3 g level b data s tream 1, 3 g level a, hd, s d): b it[0]: eav_err_d s 1 mask b it[1]: s av_err_d s 1 mask b it[2]: lnum_err_d s 1 mask b it[3]: y c r c _err_d s 1 mask b it[4]: cc r c _err_d s 1 mask b it[5]: y cs _err_d s 1 mask b it[ 6 ]: ccs _err_d s 1 mask b it[7]: reserve d b it[8]: ap_ c r c _err mask b it[9]: ff_ c r c _err mask b it[10]: vd_ s td_err_d s 1 mask r/w 0 038h error_ma s k_2 r s vd 15-7 reserve d . r 0 error_ma s k_2 6 -0 error mask for g lo b al error ve c tor (3 g level b data s tream 2 only): b it[0]: eav_err_d s 2 mask b it[1]: s av_err_d s 2 mask b it[2]: lnum_err_d s 2 mask b it[3]: y c r c _err_d s 2 mask b it[4]: cc r c _err_d s 2 mask b it[5]: y cs _err_d s 2 mask b it[ 6 ]: ccs _err_d s 2 mask r/w 0 039h - 6 bh r s vd r s vd 15-0 reserve d . r 0 0 6c h c lk_ g en r s vd 15- 6 reserve d . r/w 0 del_line_ c lk_ s el 5 c hoses b etween the in-phase (0) an d qua d rature (1) c lo c ks for ddr mo d e. r/w 0 del_line_off s et 4-0 c ontrols the offset for the d elay line. r/w 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 94 of 104 0 6 dh io_drive _ s tren g th r s vd 15- 6 reserve d . r/w 0 io_d s _ c trl_dout_m s b 5-4 drive stren g th a d justment for dout[19:10] outputs an d p c lk output: 00: 4ma; 01: 8ma; 10: 10ma(1.8v), 12ma(3.3v); 11: 12ma(1.8v), 1 6 ma(3.3v) r/w 2 io_d s _ c trl_ s tat 3-2 drive stren g th a d justment for s tat[5:0] outputs: 00: 4ma; 01: 6 ma; 10: 8ma(1.8v), 10ma(3.3v); 11: 10ma(1.8v), 12ma(3.3v) r/w 2 io_d s _ c trl_dout_l s b 1-0 drive stren g th a d justment for dout[9:0] outputs: 00: 4ma; 01: 6 ma; 10: 8ma(1.8v), 10ma(3.3v); 11: 10ma(1.8v), 12ma(3.3v) r/w 3 0 6 eh - 072h r s vd r s vd ? reserve d . r/w 0 073h eq_bypa ss r s vd 15-10 reserve d . r/w 0 eq_bypa ss 9 0: non- b ypass eq 1: b ypass eq r/w 0 r s vd 8-0 reserve d . r/w 0 074h -084h r s vd r s vd 15-0 reserve d . r/w 0 085h r s vd r s vd 15-11 reserve d . r/w 0 lo c k_noi s e _imm_in c r lo c k_noi s e_imm_in c r10ena b les extra noise-immunity on s mpte d ete c te d lo c k when hi g h b y for c in g d ete c tion of three tr s wor d s with the last two tr s wor d s havin g the same ali g nment b efore lo c kin g to s mpte. ena b le this only for auto/man = hi g h. r/w 0 r s vd r s vd 9-0 reserve d . r/w 0 table 4-18: configuration and status registers (continued) address register name bit name bit description r/w default GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 95 of 104 legend: r = rea d only ro c w = rea d only, c lear on write r/w = rea d or write w = write only 4.21 jtag test operation when the jtag/host pin of the GS2961A is set high and the smpte_bypass pin is low, the host interface port is configured for jtag test operation. in this mode, pins e7, f8, f7, and e8 become tdo, tck, tms, and tdi. in addition, the reset_trst pin operates as the test reset pin. boundary scan testing using the jtag interface is enabled in this mode. there are two ways in which jtag can be used: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly. 2. under control of a host processor for appl ications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with tri-state buffers us ed in conjunction with the jtag/host input signal. this is shown in figure 4-42 . fi g ure 4-42:in- c ir c uit j ta g table 4-19: anc extraction fifo access registers address register name bit description r/w default 800h - bffh an c _pa c ket_bank 15-0 extra c te d an c illary data 91024 wor d s. bit 15-8: most s i g nifi c ant wor d (m s w). bit 7-0: least s i g nifi c ant wor d (l s w). s ee s e c tion 4.18.8 . r0 application host cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe GS2961A GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 96 of 104 alternatively, if the test capabilities are to be used in the system, the host processor may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 4-43 . fi g ure 4-43: s ystem j ta g scan coverage is limited to digital pins only. there is no scan coverage for analog pins vco, sdo/sdo , rset, lf, and cp_res. the jtag/host pin must be held low during scan and therefore has no scan coverage. please contact your semtech representative to obtain the bsdl model for the GS2961A. 4.22 device power-up because the GS2961A is design ed to operate in a multi-v oltage environment, any power-up sequence is allowed. the charge pump, phase detector, core logic, serial digital output and i/o buffers can all be powered up in any order. note : power ramp-up time (10% to 90%) 40 s. application host cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state GS2961A GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 97 of 104 4.23 device reset note: at power-up, the device must be reset to operate correctly. in order to initialize all internal operating conditions to their default states, hold the reset_trst signal low for a minimum of t reset = 1ms after all power supplies are stable. there are no requirements for power supply sequencing. when held in reset, all device output s are driven to a high-impedance state. fi g ure 4-44:reset pulse 4.24 standby mode the standby pin reduces power to a minimum by disabling all circuits except for the register configuration. upon removal of th e signal to the standby pin, the device returns to its previous operating condition within 1 second, without requiring input from the host interface. note: in standby mode or reset, the crystal buffer output remains enabled. this allows users to reset the GS2961A devi ce without resetting other do wnstream devices that are using the same referenc e. this also allows users to put the GS2961A device in standby mode and still use the loop-through mode. s upply volta g e re s et_tr s t t reset 95% of nominal level nominal level reset reset t reset GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 98 of 104 5. application reference design 5.1 high gain adaptive cable equalizers the GS2961A has an integrated adaptive cable equalizer. in order to extend the cable length that an equalizer will remain operational at, it is necessary for the equalizer to have high gain. a video cable equalizer must provide wide band gain over a range of frequencies in order to accommodate the range of data rates and signal patterns that are present in a smpte compliant serial video stream. small levels of signal or noise present at the input pi ns of the GS2961A may cause chatter at the output. in order to prevent this from happening, particular attention must be paid to board layout. 5.2 pcb layout special attention must be paid to compon ent layout when desi gning serial digital interfaces for hdtv. an fr-4 dielectric can be used, however, controlled impedance transmission lines are required for pcb traces longer than approximately 1cm. note the following pcb artwork features used to optimize performance: ? pcb trace width for 3gb/s rate signals is closely matched to smt component width to minimize reflections due to change in trace impedance. ? the pcb ground plane is removed under the GS2961A input components to minimize parasitic capacitance. ? high speed traces are curved to minimize impedance changes. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 99 of 104 5.3 typical application circuit cd_vdd host interface & control cs10-27.000m 16p 16p cd_vdd 470n +1.2v_a 0r 0r 10n +1.2v 10n 10n 10n 10n 5. for impedance controlled signal layout refer to pcb layout guide. io_vdd +1.2v dout[19:0] 10n power filtering 10n 10n sdin_tdi dnp sclk_tck 4u7 10n 49r9 49r9 close to pin 1 & 2 of gs2978 cs_tms +1.2v_a io_vdd +3.3v_a r7 105r +1.2v c18 33u +1.2v_a locked (default, programmable) r19 dnp +3.3v_a 22r 0r 10n 10n place close to GS2961A 1 3 2 ucbbje20-1 cd_disableb y /1anc (default, programmable) pclk 22r data_errorb (default, programmable) 1u 22r sdi input h/hsync (default, programmable) 1u a_gnd 22r 10n cd slew rate select vbg a1 lf a2 lb_cont a3 vco_vdd a4 stat0 a5 stat1 a6 stat2 b5 stat3 b6 stat4 c5 stat5 c6 io_vdd a7 pclk a8 dout 0 k8 dout 1 j8 dout 2 k9 dout 3 k10 dout 4 j9 dout 5 j10 dout 6 h9 dout 7 h10 dout 8 f9 dout 9 f10 dout 10 e9 dout 11 e10 dout 12 c8 dout 13 c10 dout 14 c9 dout 15 b10 dout 16 b9 dout 17 a10 dout 18 a9 dout 19 b8 a_vdd b1 pll_vdd b2 rsv b3 vco_gnd b4 io_gnd b7 sdi c1 a_gnd c2 pll_vdd c3 pll_vdd c4 reset_trst c7 sdi d1 a_gnd d2 a_gnd d3 pll_gnd d4 core_gnd d5 core_vdd d6 sw_en d7 jtag/host d8 io_gnd d9 io_vdd d10 eq_vdd e1 a_gnd e3 pll_gnd e4 core_gnd e5 core_vdd e6 sdout_tdo e7 sdin_tdi e8 f1 agcn f2 a_gnd f3 pll_gnd f4 core_gnd f5 core_vdd f6 cs_tms f7 sclk_tck f8 g1 g2 rc_by p g3 rsv g4 core_gnd g5 core_vdd g6 smpte_by pass g7 dvb_asi g8 io_gnd g9 io_vdd g10 buf_vdd h1 buf_gnd h2 h4 ti m_861 h5 xtal_out h6 20bit/10bit h7 ioproc_en/dis h8 sdo j1 sdo_en/dis j2 j3 j4 j5 xtal2 j6 io_gnd j7 sdo k1 standby k2 k3 k4 k5 xtal1 k6 io_vdd k7 sdi_gnd e2 GS2961Aibe3 smpte_by pass 1u place close to GS2961A +3.3v_a 10n v/vsy nc (default, programmable) 22r 1u f/de (default, programmable) 22r 22r 22r 3. for analog power and ground isolation refer to pcb layout guide. 4. for critital 3g signal layout refer to pcb layout guide. dvb_asi power decoupling 22r place close to GS2961A 22r sdout_tdo sw_en 1u 22r 1u 22r ioproc_en/dis 75-ohm traces cd_disableb 22r 75r 4u7 sdi loop-through output 20bit/10bit 75r 5n6 10n +3.3v_a 10n 10n 1 3 2 ucbbje20-1 22r rc_byp 75r 75r io_vdd 1u 22r jtag/host 75r 6n2 75r 22r 1u 37r4 1u 22r standby reset_trst 22r 2. the value of the series resistors on video data, clock, and timing connections should be determined by board signal integrity test. 22r 22r 22r sdo_en/dis 22r +3.3v tp cd_vdd 0r 10n 10n 47n sdi 2 vee 3 nc 14 rset 4 nc 16 sd/hd 10 sdo 11 sdi 1 vcc 9 sdo 12 nc 13 disable 6 rsvd 7 nc 8 nc 15 nc 5 tab 17 gs2978-cne3 10n +1.2v_a 10n 10n 22r 10n 10n dout[19:0] tim_861 22r 750r 1. dnp (do not populate). notes: 1u video data, clock & timing output a_gnd a_gnd a_gnd a_gnd a_gnd a_gnd a_gnd a_gnd a_gnd cd_vdd a_gnd a_gnd a_gnd a_gnd a_gnd a_gnd 470n agcp core_gnd rsv rsv rsv rsv rsv rsv rsv a_gnd core_gnd h3 a_gnd GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 100 of 104 6. references & relevant standards s mpte 125m c omponent vi d eo si g nal 4:2:2 ? b it parallel interfa c e s mpte 259m 10- b it 4:2:2 c omponent an d 4fs c c omposite di g ital s i g nals - s erial di g ital interfa c e s mpte 2 6 0m 1125 / 6 0 hi g h d efinition pro d u c tion system ? d i g ital representation an d b it parallel interfa c e s mpte 2 6 7m bit parallel d i g ital interfa c e ? c omponent vi d eo si g nal 4:2:2 1 6 x 9 aspe c t ratio s mpte 272m formattin g ae s /ebu au d io an d auxiliary data into di g ital vi d eo an c illary data s pa c e s mpte 274m 1920 x 1080 s c annin g analo g an d parallel d i g ital interfa c es for multiple pi c ture rates s mpte 291m an c illary data pa c ket an d s pa c e formattin g s mpte 292m bit- s erial di g ital interfa c e for hi g h-definition television s ystems s mpte 293m 720 x 483 a c tive line at 59.94hz pro g ressive s c an pro d u c tion ? d i g ital representation s mpte 29 6 m 1280 x 720 s c annin g , analo g an d d i g ital representation an d analo g interfa c e s mpte 299m 24-bit di g ital au d io format for hdtv bit- s erial interfa c e s mpte 305m s erial data transport interfa c e s mpte 348m hi g h data-rate s erial data transport interfa c e (hd- s dti) s mpte 352m vi d eo payloa d i d entifi c ation for di g ital television interfa c es s mpte 372m dual link 292m interfa c e for 1920 x 1080 pi c ture raster s mpte 424m television - 3 gb /s s i g nal/data s erial interfa c e s mpte 425m television - 3 gb /s s i g nal/data s erial interfa c e - s our c e ima g e format mappin g s mpte rp1 6 5 error dete c tion c he c kwor d s an d s tatus fla g s for use in bit- s erial di g ital interfa c es for television s mpte rp1 6 8 definition of verti c al interval s wit c hin g point for s yn c hronous vi d eo s wit c hin g c ea 8 6 1vi d eo timin g requirements GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 101 of 104 7. package & ordering information 7.1 package dimensions 0.366 (0.366) top view bottom view pin 1 corner 1 2 345 6 789 10 a b c d e f g h j k * the ball diameter, ball pitch, stand-off & package thickness are different from jedec spec m0192 (low profile bga family) 0.700.05 seating plane 0.25 c c package outline 100l lbga package size: 11 x 11 x 1.71mm 1.00 0.50 0.70 ball pitch: ball diameter: mold thickness: substrate thickness: 10 a b c d e f g h j k 1 2 3 4 5 6 7 8 9 b a 0.20(4x) 0.15 1.700 ref. 0.30 ~ 0.50 9.00 1.00 110.10 pin 1 corner ab c c 0.10 0.25 0.40~0.60(100x) 1.00 9.00 110.10 GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 102 of 104 7.2 packaging data 7.3 marking diagram table 7-1: packaging data parameter value pa c ka g e type 11mm x 11mm 100- b all lb g a pa c ka g e drawin g referen c e j ede c m0192 (with ex c eptions note d in pa c ka g e dimensions on pa g e 101 ). moisture s ensitivity level 3 j un c tion to c ase thermal resistan c e, j- c 15.4 c /w j un c tion to air thermal resistan c e, j-a (at zero airflow) 37.1 c /w j un c tion to boar d thermal resistan c e, j- b 2 6 .4 c /w psi, 0.4 c /w p b -free an d roh s c ompliant yes GS2961A xxxxe3 yyww pin 1 id xxxx - last 4 digits (excluding decimal) of sap batch assembly (fin) as listed on packing slip. e3 - pb-free & green indicator yyww - date code GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 103 of 104 7.4 solder reflow profiles the GS2961A is available in a pb-free package. it is re commended that the pb-free package be soldered with pb-free paste using the reflow profile shown in figure 7-1 . fi g ure 7-1:p b -free s ol d er reflow profile 7.5 ordering information revision history 25c 150c 200c 217c 260c 250c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3c/sec max 6c/sec max part number package pb-free temperature range gs 29 6 1aibe3 100- b all b g a yes -20 c to 85 c version ecr pcn date changes and/or modifications 2 1584 6 8? s eptem b er 2012 c han g es throu g hout the d o c ument. 1 154880 ? s eptem b er 2010 define d b its noninv (001h-14) an d di s b_autdet (001h-13) in ta b le 4-18 c onfi g uration an d s tatus re g isters . 0 1537 6 9 ? may 2010 new do c ument. ? semtech 2012 all rights reserved. reproduction in whole or in part is pr ohibited without the prior writt en consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under pa tent or other industrial or intellectual property rights. semtech assumes no responsibili ty or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the sp ecified maximum ratings or operation outside the specified range. semtech products are not designed, intended, authori zed or warranted to be suitable for use in life-support applications, devices or systems or other critical applicatio ns. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized applic ation, the customer shall indemnify and hold semtech and its officers, employees, subs idiaries, affiliates, and distributors harmless against all claims, costs damages and atto rney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners . document identification data sheet information relating to this product and the application or design described herein is believed to be reliable, ho wever such information is provided as a guide only and semtech assumes no liability for any errors in this document, or for the application or design described herein. semtech reserves the right to make changes to the product or this document at any time without notice. GS2961A 3gb/s, hd, sd sdi integrated receiver data sheet 54385 - 2 september 2012 104 of 104 104 contact information semtech corporation gennum products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111, fax: (805) 498-3804 www.semtech.com caution ele c tro s tati c s en s itive devi c e s do not open pa c ka g e s or handle ex c ept at a s tati c -free work s tation |
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